From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 21 Jun 2019 04:53:27 +0000 (-0700)
Subject: Fix gcc warning of potentially uninitialised
X-Git-Tag: working-ls180~1208^2~125
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=06bf2ea5621ba5f18aea0fbcb788a041309e0148;p=yosys.git

Fix gcc warning of potentially uninitialised
---

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 3f7efa800..b904b66c1 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -522,7 +522,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 		for (auto c : mapped_mod->cells())
 		{
 			if (c->type == "$_NOT_") {
-				RTLIL::Cell *cell;
+				RTLIL::Cell *cell = nullptr;
 				RTLIL::SigBit a_bit = c->getPort("\\A").as_bit();
 				RTLIL::SigBit y_bit = c->getPort("\\Y").as_bit();
 				if (!a_bit.wire) {
@@ -576,7 +576,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 					cell->setPort("\\Y", RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset));
 					cell_stats[RTLIL::unescape_id(c->type)]++;
 				}
-				if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
+				if (cell && markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
 				continue;
 			}
 			cell_stats[RTLIL::unescape_id(c->type)]++;