From: whitequark <whitequark@whitequark.org>
Date: Thu, 16 Apr 2020 16:45:02 +0000 (+0000)
Subject: cxxrtl: make ROMs writable, document memory::operator[].
X-Git-Tag: working-ls180~627^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=06c0338f2c19ca50675f3928de7fa19b05d304c4;p=yosys.git

cxxrtl: make ROMs writable, document memory::operator[].

There is no practical benefit from using `const memory` for ROMs;
it uses an std::vector internally, which prevents contemporary
compilers from constant-propagating ROM contents. (It is not clear
whether they are permitted to do so.)

However, there is a major benefit from using non-const `memory` for
ROMs, which is the ability to dynamically fill the ROM for each
individual simulation.
---

diff --git a/backends/cxxrtl/cxxrtl.cc b/backends/cxxrtl/cxxrtl.cc
index 8f7f9d7a3..e4fa430f3 100644
--- a/backends/cxxrtl/cxxrtl.cc
+++ b/backends/cxxrtl/cxxrtl.cc
@@ -1166,8 +1166,7 @@ struct CxxrtlWorker {
 		});
 
 		dump_attrs(memory);
-		f << indent << (writable_memories[memory] ? "" : "const ")
-		            << "memory<" << memory->width << "> " << mangle(memory)
+		f << indent << "memory<" << memory->width << "> " << mangle(memory)
 		            << " { " << memory->size << "u";
 		if (init_cells.empty()) {
 			f << " };\n";
diff --git a/backends/cxxrtl/cxxrtl.h b/backends/cxxrtl/cxxrtl.h
index 593c31c28..fd390db79 100644
--- a/backends/cxxrtl/cxxrtl.h
+++ b/backends/cxxrtl/cxxrtl.h
@@ -604,12 +604,15 @@ struct memory {
 		auto _ = {std::move(std::begin(init.data), std::end(init.data), data.begin() + init.offset)...};
 	}
 
-	value<Width> &operator [](size_t index) {
+	// An operator for direct memory reads. May be used at any time during the simulation.
+	const value<Width> &operator [](size_t index) const {
 		assert(index < data.size());
 		return data[index];
 	}
 
-	const value<Width> &operator [](size_t index) const {
+	// An operator for direct memory writes. May only be used before the simulation is started. If used
+	// after the simulation is started, the design may malfunction.
+	value<Width> &operator [](size_t index) {
 		assert(index < data.size());
 		return data[index];
 	}