From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 9 Jun 2020 22:12:58 +0000 (+0100)
Subject: add means to get pc and other qemu registers
X-Git-Tag: div_pipeline~443
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=06ce978548a95a8a6d94cfe826954cc73d9e4a9f;p=soc.git

add means to get pc and other qemu registers
---

diff --git a/src/soc/simulator/qemu.py b/src/soc/simulator/qemu.py
index 1669dafe..d45c17c8 100644
--- a/src/soc/simulator/qemu.py
+++ b/src/soc/simulator/qemu.py
@@ -31,14 +31,26 @@ class QemuController:
     def get_registers(self):
         return self.gdb.write('-data-list-register-values x')
 
-    def get_register(self, num):
-        res = self.gdb.write('-data-list-register-values x {}'.format(num),timeout_sec=1.0) # increase this timeout if needed
+    def _get_register(self, fmt):
+        res = self.gdb.write('-data-list-register-values '+fmt,
+                             timeout_sec=1.0) # increase this timeout if needed
         for x in res:
             if(x["type"]=="result"):
                 assert 'register-values' in x['payload']
                 return int(x['payload']['register-values'][0]['value'], 0)
         return None
 
+    def get_pc(self): return self._get_register('pc')
+    def get_cr(self): return self._get_register('cnd')
+    def get_xer(self): return self._get_register('xer')
+    def get_msr(self): return self._get_register('msr')
+    def get_lr(self): return self._get_register('lr')
+    def get_fpscr(self): return self._get_register('fpscr')
+    def get_ctr(self): return self._get_register('cnt') # probably
+
+    def get_register(self, num):
+        return self._get_register('x {}'.format(num))
+
     def step(self):
         return self.gdb.write('-exec-next-instruction')