From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 1 Jul 2019 16:45:22 +0000 (-0700)
Subject: Merge remote-tracking branch 'origin/master' into xc7mux
X-Git-Tag: working-ls180~1208^2~37
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=06dcf7d08d10ab5cad164287b7ff7c75a96548ac;p=yosys.git

Merge remote-tracking branch 'origin/master' into xc7mux
---

06dcf7d08d10ab5cad164287b7ff7c75a96548ac
diff --cc CHANGELOG
index e380c6d52,5535ce418..7ac418160
--- a/CHANGELOG
+++ b/CHANGELOG
@@@ -2,13 -2,18 +2,24 @@@
  List of major changes and improvements between releases
  =======================================================
  
 +Yosys 0.9 .. Yosys 0.9-dev
 +--------------------------
 +
 + * Various
 +    - Added "script -select"
 +
  
+ Yosys 0.9 .. Yosys 0.9-dev
+ --------------------------
+ 
+  * Various
+     - Added "write_xaiger" backend
+     - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
+     - Added "synth_xilinx -abc9" (experimental)
+     - Added "synth_ice40 -abc9" (experimental)
+     - Added "synth -abc9" (experimental)
+ 
+ 
  Yosys 0.8 .. Yosys 0.8-dev
  --------------------------
  
@@@ -32,13 -37,7 +43,8 @@@
      - Added "synth_xilinx -nocarry"
      - Added "synth_xilinx -nowidelut"
      - Added "synth_ecp5 -nowidelut"
-     - Added "write_xaiger" backend
-     - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
-     - Added "synth_xilinx -abc9" (experimental)
-     - Added "synth_ice40 -abc9" (experimental)
-     - Added "synth -abc9" (experimental)
      - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
 +    - "synth_xilinx" to now infer wide multiplexers (-widemux <min> to enable)
      - Fixed sign extension of unsized constants with 'bx and 'bz MSB