From: Paul Mackerras Date: Sat, 4 Sep 2021 09:36:02 +0000 (+1000) Subject: decode1: Fix maddld and maddhdu to not set CR0 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=06e07c69a82f81738331e12dc5dee01ba942a148;p=microwatt.git decode1: Fix maddld and maddhdu to not set CR0 Signed-off-by: Paul Mackerras --- diff --git a/decode1.vhdl b/decode1.vhdl index 0866b5b..b399673 100644 --- a/decode1.vhdl +++ b/decode1.vhdl @@ -133,9 +133,9 @@ architecture behaviour of decode1 is constant decode_op_4_array : op_4_subop_array_t := ( -- unit fac internal in1 in2 in3 out CR CR inv inv cry cry ldst BR sgn upd rsrv 32b sgn rc lk sgl rpt -- op in out A out in out len ext pipe - 2#110000# => (ALU, NONE, OP_MUL_H64, RA, RB, RCR, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', RC, '0', '0', NONE), -- maddhd - 2#110001# => (ALU, NONE, OP_MUL_H64, RA, RB, RCR, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', NONE), -- maddhdu - 2#110011# => (ALU, NONE, OP_MUL_L64, RA, RB, RCR, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', RC, '0', '0', NONE), -- maddld + 2#110000# => (ALU, NONE, OP_MUL_H64, RA, RB, RCR, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', NONE, '0', '0', NONE), -- maddhd + 2#110001# => (ALU, NONE, OP_MUL_H64, RA, RB, RCR, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', NONE), -- maddhdu + 2#110011# => (ALU, NONE, OP_MUL_L64, RA, RB, RCR, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', NONE, '0', '0', NONE), -- maddld others => decode_rom_init );