From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 25 Feb 2009 18:19:22 +0000 (-0800)
Subject: X86: Implement a basic prefetch instruction.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=06ff83e1b9aa2a00af4f66fae7c9fce2ac36394a;p=gem5.git

X86: Implement a basic prefetch instruction.
---

diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index fa49c55d3..a0a08df8f 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -281,7 +281,7 @@
                 0x2: Inst::UD2();
                 0x3: Inst::UD2();
                 0x4: Inst::UD2();
-                0x5: prefetch();
+                0x5: Inst::PREFETCH(Mb);
                 0x6: FailUnimpl::femms();
                 0x7: FailUnimpl::threednow();
             }
@@ -335,7 +335,7 @@
                 //group17();
                 0x0: decode MODRM_REG {
                     0x0: prefetch_nta();
-                    0x1: prefetch_t0();
+                    0x1: Inst::PREFETCH_T0(Mb);
                     0x2: prefetch_t1();
                     0x3: prefetch_t2();
                     default: Inst::HINT_NOP();
diff --git a/src/arch/x86/isa/includes.isa b/src/arch/x86/isa/includes.isa
index 10bac86ed..8626f117a 100644
--- a/src/arch/x86/isa/includes.isa
+++ b/src/arch/x86/isa/includes.isa
@@ -157,6 +157,7 @@ output exec {{
 #include "sim/sim_exit.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
+#include "mem/request.hh"
 #include "sim/pseudo_inst.hh"
 
 using namespace X86ISA;
diff --git a/src/arch/x86/isa/insts/general_purpose/cache_and_memory_management.py b/src/arch/x86/isa/insts/general_purpose/cache_and_memory_management.py
index 08b842825..dbd2d8b84 100644
--- a/src/arch/x86/isa/insts/general_purpose/cache_and_memory_management.py
+++ b/src/arch/x86/isa/insts/general_purpose/cache_and_memory_management.py
@@ -53,7 +53,31 @@
 #
 # Authors: Gabe Black
 
-microcode = ""
+microcode = '''
+def macroop PREFETCH_M
+{
+    ld t0, seg, sib, disp, dataSize=1, prefetch=True
+};
+
+def macroop PREFETCH_P
+{
+    rdip t7
+    ld t0, seg, riprel, disp, dataSize=1, prefetch=True
+};
+
+def macroop PREFETCH_T0_M
+{
+    ld t0, seg, sib, disp, dataSize=1, prefetch=True
+};
+
+def macroop PREFETCH_T0_P
+{
+    rdip t7
+    ld t0, seg, riprel, disp, dataSize=1, prefetch=True
+};
+
+'''
+
 #let {{
 #    class LFENCE(Inst):
 #       "GenFault ${new UnimpInstFault}"
@@ -63,8 +87,6 @@ microcode = ""
 #       "GenFault ${new UnimpInstFault}"
 #    class PREFETCHlevel(Inst):
 #       "GenFault ${new UnimpInstFault}"
-#    class PREFETCH(Inst):
-#       "GenFault ${new UnimpInstFault}"
 #    class PREFETCHW(Inst):
 #       "GenFault ${new UnimpInstFault}"
 #    class CLFLUSH(Inst):
diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa
index a1aaddfe2..3bc238174 100644
--- a/src/arch/x86/isa/microops/ldstop.isa
+++ b/src/arch/x86/isa/microops/ldstop.isa
@@ -155,9 +155,11 @@ def template MicroLoadExecute {{
 
         fault = read(xc, EA, Mem, memFlags);
 
-        if(fault == NoFault)
-        {
+        if (fault == NoFault) {
             %(code)s;
+        } else if (memFlags & Request::PF_EXCLUSIVE) {
+            // For prefetches, ignore any faults/exceptions.
+            return NoFault;
         }
         if(fault == NoFault)
         {
@@ -361,7 +363,7 @@ def template MicroLdStOpConstructor {{
 let {{
     class LdStOp(X86Microop):
         def __init__(self, data, segment, addr, disp,
-                dataSize, addressSize, baseFlags, atCPL0):
+                dataSize, addressSize, baseFlags, atCPL0, prefetch):
             self.data = data
             [self.scale, self.index, self.base] = addr
             self.disp = disp
@@ -371,6 +373,8 @@ let {{
             self.memFlags = baseFlags
             if atCPL0:
                 self.memFlags += " | (CPL0FlagBit << FlagShift)"
+            if prefetch:
+                self.memFlags += " | Request::PF_EXCLUSIVE"
 
         def getAllocator(self, *microFlags):
             allocator = '''new %(class_name)s(machInst, macrocodeBlock
@@ -420,9 +424,10 @@ let {{
             def __init__(self, data, segment, addr, disp = 0,
                     dataSize="env.dataSize",
                     addressSize="env.addressSize",
-                    atCPL0=False):
+                    atCPL0=False, prefetch=False):
                 super(LoadOp, self).__init__(data, segment, addr,
-                        disp, dataSize, addressSize, mem_flags, atCPL0)
+                        disp, dataSize, addressSize, mem_flags,
+                        atCPL0, prefetch)
                 self.className = Name
                 self.mnemonic = name
 
@@ -460,7 +465,7 @@ let {{
                     addressSize="env.addressSize",
                     atCPL0=False):
                 super(StoreOp, self).__init__(data, segment, addr,
-                        disp, dataSize, addressSize, mem_flags, atCPL0)
+                        disp, dataSize, addressSize, mem_flags, atCPL0, False)
                 self.className = Name
                 self.mnemonic = name
 
@@ -484,7 +489,7 @@ let {{
         def __init__(self, data, segment, addr, disp = 0,
                 dataSize="env.dataSize", addressSize="env.addressSize"):
             super(LeaOp, self).__init__(data, segment,
-                    addr, disp, dataSize, addressSize, "0", False)
+                    addr, disp, dataSize, addressSize, "0", False, False)
             self.className = "Lea"
             self.mnemonic = "lea"
 
@@ -503,7 +508,7 @@ let {{
                 dataSize="env.dataSize",
                 addressSize="env.addressSize"):
             super(TiaOp, self).__init__("NUM_INTREGS", segment,
-                    addr, disp, dataSize, addressSize, "0", False)
+                    addr, disp, dataSize, addressSize, "0", False, False)
             self.className = "Tia"
             self.mnemonic = "tia"
 
@@ -514,7 +519,7 @@ let {{
                 dataSize="env.dataSize",
                 addressSize="env.addressSize", atCPL0=False):
             super(CdaOp, self).__init__("NUM_INTREGS", segment,
-                    addr, disp, dataSize, addressSize, "0", atCPL0)
+                    addr, disp, dataSize, addressSize, "0", atCPL0, False)
             self.className = "Cda"
             self.mnemonic = "cda"