From: lkcl <lkcl@web>
Date: Sat, 7 May 2022 12:22:49 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2329
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=070ba5495e9f6557ff1fc35b5b8c77df3ed7c031;p=libreriscv.git

---

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index a7a8dd46e..4b392ee00 100644
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -584,7 +584,7 @@ schedules to more than just registers
 
 OpenCAPI is a deterministic high-performance, high-bandwidth, low-latency
 cache-coherent Memory-access Protocol that is integrated into IBM's Supercomputing-class POWER9 and POWER10 processors. POWER10 *only*
-has OpenCAPI Memory interfaces, and requires an OpenCAPI-to-DDR4/5 Bridge PHY
+has OpenCAPI Memory interfaces, and requires an OMI-to-DDR4/5 Bridge PHY
 to connect to standard DIMMs.
 
 Extra-V appears to be a remarkable research project that, by leveraging