From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 3 Mar 2015 09:39:31 +0000 (+0100)
Subject: targets: keep the SPI flash core even if with_rom is enabled, so that flash booting... 
X-Git-Tag: 24jan2021_ls180~2513
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0716dadaf2cf616eeab6647da6d7c6d8d48794c7;p=litex.git

targets: keep the SPI flash core even if with_rom is enabled, so that flash booting in the BIOS still works
---

diff --git a/targets/kc705.py b/targets/kc705.py
index b3587466..ff3a8232 100644
--- a/targets/kc705.py
+++ b/targets/kc705.py
@@ -100,15 +100,16 @@ class BaseSoC(SDRAMSoC):
 		self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"), memtype="DDR3")
 		self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing)
 
+		spiflash_pads = platform.request("spiflash")
+		spiflash_pads.clk = Signal()
+		self.specials += Instance("STARTUPE2",
+			i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0,
+			i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
+		self.submodules.spiflash = spiflash.SpiFlash(spiflash_pads, dummy=11, div=2)
+		self.flash_boot_address = 0xb00000
+
 		# If not in ROM, BIOS is in SPI flash
 		if not self.with_rom:
-			spiflash_pads = platform.request("spiflash")
-			spiflash_pads.clk = Signal()
-			self.specials += Instance("STARTUPE2",
-				i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0,
-				i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
-			self.submodules.spiflash = spiflash.SpiFlash(spiflash_pads, dummy=11, div=2)
-			self.flash_boot_address = 0xb00000
 			self.register_rom(self.spiflash.bus)
 
 class MiniSoC(BaseSoC):
diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py
index 865b2d40..498237bd 100644
--- a/targets/mlabs_video.py
+++ b/targets/mlabs_video.py
@@ -59,11 +59,12 @@ class BaseSoC(SDRAMSoC):
 			rd_bitslip=0, wr_bitslip=3, dqs_ddr_alignment="C1")
 		self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing)
 
+		self.submodules.norflash = norflash16.NorFlash16(platform.request("norflash"),
+			self.ns(110), self.ns(50))
+		self.flash_boot_address = 0x001a0000
+
 		# If not in ROM, BIOS is in // NOR flash
 		if not self.with_rom:
-			self.submodules.norflash = norflash16.NorFlash16(platform.request("norflash"),
-				self.ns(110), self.ns(50))
-			self.flash_boot_address = 0x001a0000
 			self.register_rom(self.norflash.bus)
 
 		self.submodules.crg = mxcrg.MXCRG(_MXClockPads(platform), self.clk_freq)
diff --git a/targets/pipistrello.py b/targets/pipistrello.py
index 104768b9..61b3d172 100644
--- a/targets/pipistrello.py
+++ b/targets/pipistrello.py
@@ -122,10 +122,12 @@ class BaseSoC(SDRAMSoC):
 PIN "BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE;
 """)
 		self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing)
+
+		self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash4x"), dummy=11, div=2)
+		self.flash_boot_address = 0x180000
+
 		# If not in ROM, BIOS is in SPI flash
 		if not self.with_rom:
-			self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash4x"), dummy=11, div=2)
-			self.flash_boot_address = 0x180000
 			self.register_rom(self.spiflash.bus)
 
 default_subtarget = BaseSoC
diff --git a/targets/ppro.py b/targets/ppro.py
index 142d2b4c..1dfad435 100644
--- a/targets/ppro.py
+++ b/targets/ppro.py
@@ -92,10 +92,11 @@ class BaseSoC(SDRAMSoC):
 		self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"))
 		self.register_sdram_phy(self.sdrphy, sdram_geom, sdram_timing)
 
+		self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"), dummy=4, div=6)
+		self.flash_boot_address = 0x70000
+
 		# If not in ROM, BIOS is in SPI flash
 		if not self.with_rom:
-			self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"), dummy=4, div=6)
-			self.flash_boot_address = 0x70000
 			self.register_rom(self.spiflash.bus)
 
 default_subtarget = BaseSoC