From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 18 Jul 2019 20:18:04 +0000 (-0700)
Subject: Fix xilinx_dsp index cast
X-Git-Tag: working-ls180~1039^2~340
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0727b2c902df37fbbf2fe9acc31d96ce84fa88a7;p=yosys.git

Fix xilinx_dsp index cast
---

diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index 60e972615..51fd733d4 100644
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -11,7 +11,7 @@ match ffA
 	select ffA->type.in($dff, $dffe)
 	select param(ffA, \CLK_POLARITY).as_bool()
 	// select nusers(port(ffA, \Q)) == 2
-	index <SigSpec> port(ffA, \Q).to_sigbit_pool() === port(dsp, \A).remove_const().to_sigbit_pool()
+	index <pool<SigBit>> port(ffA, \Q).to_sigbit_pool() === port(dsp, \A).remove_const().to_sigbit_pool()
 	// DSP48E1 does not support clock inversion
 	optional
 endmatch
@@ -25,7 +25,7 @@ match ffB
 	select ffB->type.in($dff, $dffe)
 	select param(ffB, \CLK_POLARITY).as_bool()
 	// select nusers(port(ffB, \Q)) == 2
-	index <SigSpec> port(ffB, \Q).to_sigbit_pool() === port(dsp, \B).remove_const().to_sigbit_pool()
+	index <pool<SigBit>> port(ffB, \Q).to_sigbit_pool() === port(dsp, \B).remove_const().to_sigbit_pool()
 	optional
 endmatch