From: David Shah <dave@ds0.me>
Date: Wed, 31 Oct 2018 13:29:35 +0000 (+0000)
Subject: ulx3s: Connect SDRAM clock
X-Git-Tag: 24jan2021_ls180~1521^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0729b3a059b1991405de8b345b3130499c874ef5;p=litex.git

ulx3s: Connect SDRAM clock

Signed-off-by: David Shah <dave@ds0.me>
---

diff --git a/litex/boards/targets/ulx3s.py b/litex/boards/targets/ulx3s.py
index 6d8a4e07..af1aa19e 100755
--- a/litex/boards/targets/ulx3s.py
+++ b/litex/boards/targets/ulx3s.py
@@ -45,6 +45,8 @@ class _CRG(Module):
                 o_Z=new_sdram_ps_clk)
             sdram_ps_clk = new_sdram_ps_clk
         self.comb += self.cd_sys_ps.clk.eq(sdram_ps_clk)
+        sdram_clock = platform.request("sdram_clock")
+        self.comb += sdram_clock.eq(sdram_ps_clk)
 
         # Stop ESP32 from resetting FPGA
         wifi_gpio0 = platform.request("wifi_gpio0")