From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Wed, 4 Mar 2015 00:46:24 +0000 (+0000)
Subject: litesata: fix permissions and imports
X-Git-Tag: 24jan2021_ls180~2511
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=073641faa1942b41b0f143d3b164b95ef8214cda;p=litex.git

litesata: fix permissions and imports
---

diff --git a/misoclib/mem/litesata/example_designs/build/.keep_me b/misoclib/mem/litesata/example_designs/build/.keep_me
new file mode 100644
index 00000000..e69de29b
diff --git a/misoclib/mem/litesata/example_designs/make.py b/misoclib/mem/litesata/example_designs/make.py
old mode 100644
new mode 100755
diff --git a/misoclib/mem/litesata/example_designs/platforms/verilog_backend.py b/misoclib/mem/litesata/example_designs/platforms/verilog_backend.py
index f531c901..7302a0eb 100644
--- a/misoclib/mem/litesata/example_designs/platforms/verilog_backend.py
+++ b/misoclib/mem/litesata/example_designs/platforms/verilog_backend.py
@@ -1,6 +1,6 @@
 from mibuild.generic_platform import *
-from mibuild.xilinx_common import CRG_DS
-from mibuild.xilinx_vivado import XilinxVivadoPlatform
+from mibuild.xilinx.common import CRG_DS
+from mibuild.xilinx.vivado import XilinxVivadoPlatform
 
 _io = [
 	("sys_clk", 0, Pins("X")),