From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 29 Apr 2022 09:47:03 +0000 (+0100)
Subject: higher bits need to be checked for overflow not lower
X-Git-Tag: sv_maxu_works-initial~455
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=073981b64b750059e784f82fd35aa809eb2e5a69;p=openpower-isa.git

higher bits need to be checked for overflow not lower
after swapping RC and RA, RC is now in the higher bits of divmod2du
---

diff --git a/openpower/isa/svfixedarith.mdwn b/openpower/isa/svfixedarith.mdwn
index cf883450..cd2b320a 100644
--- a/openpower/isa/svfixedarith.mdwn
+++ b/openpower/isa/svfixedarith.mdwn
@@ -29,7 +29,7 @@ Pseudo-code:
     <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below   -->
     <!-- bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+VL -->
     <!-- bit 8 of EXTRA is set  : RS.[s|v]=RC.[s|v]    -->
-    if ((RA) <u (RB)) & ((RB) != [0]*XLEN) then
+    if ((RC) <u (RB)) & ((RB) != [0]*XLEN) then
         dividend[0:(XLEN*2)-1] <- (RC) || (RA)
         divisor[0:(XLEN*2)-1] <- [0]*XLEN || (RB)
         result <- dividend / divisor