From: Cesar Strauss <cestrauss@gmail.com>
Date: Sat, 16 Apr 2022 17:33:04 +0000 (-0300)
Subject: Add port declarations to the SRAM wrappers
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=07441462940dcf8412fef9ed2119a905bd084659;p=soc.git

Add port declarations to the SRAM wrappers
---

diff --git a/src/soc/regfile/sram_wrapper.py b/src/soc/regfile/sram_wrapper.py
index 5a455b81..297a935f 100644
--- a/src/soc/regfile/sram_wrapper.py
+++ b/src/soc/regfile/sram_wrapper.py
@@ -340,6 +340,16 @@ class PhasedDualPortRegfile(Elaboratable):
 
         return m
 
+    def ports(self):
+        return [
+            self.wr_addr_i,
+            self.wr_data_i,
+            self.wr_we_i,
+            self.rd_addr_i,
+            self.rd_data_o,
+            self.phase
+        ]
+
 
 class PhasedDualPortRegfileTestCase(FHDLTestCase):
 
@@ -660,6 +670,15 @@ class DualPortRegfile(Elaboratable):
                                    == self.dbg_wrote_phase)
         return m
 
+    def ports(self):
+        return [
+            self.wr_addr_i,
+            self.wr_data_i,
+            self.wr_we_i,
+            self.rd_addr_i,
+            self.rd_data_o
+        ]
+
 
 class DualPortRegfileTestCase(FHDLTestCase):