From: Luke Kenneth Casson Leighton Date: Thu, 27 Apr 2023 09:39:43 +0000 (+0100) Subject: experiment with dividers X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=075658965073f3fb9fa312d7372c7bd6b5171b89;p=libreriscv.git experiment with dividers --- diff --git a/openpower/sv/cookbook/chacha20.mdwn b/openpower/sv/cookbook/chacha20.mdwn index 44ae30d2a..56373bc57 100644 --- a/openpower/sv/cookbook/chacha20.mdwn +++ b/openpower/sv/cookbook/chacha20.mdwn @@ -141,8 +141,11 @@ Let's assume the values `x` in the registers 24-36 | h1 | r0 | r1 | r2 | r3 | |--------|-----|-----|-----|-----| | GPR 24 | x0 | x1 | x2 | x3 | +|--------|-----|-----|-----|-----| | GPR 28 | x4 | x5 | x6 | x7 | +|--------|-----|-----|-----|-----| | GPR 32 | x8 | x9 | x10 | x11 | +|--------|-----|-----|-----|-----| | GPR 36 | x12 | x13 | x14 | x15 | So for the addition in Vertical-First mode, `RT` (and `RA` as they are the