From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 25 Sep 2022 12:48:23 +0000 (+0100)
Subject: add dz/sz assertion in is_bc mode
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0766fdc93e48a2212751a1857585541037fb119f;p=openpower-isa.git

add dz/sz assertion in is_bc mode
---

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index 59611cc0..37fb7566 100644
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -1186,6 +1186,8 @@ class SVP64Asm:
                 elif encmode == 'cti':
                     svp64_rm.branch.CTR = 1
                     svp64_rm.branch.ctr.CTi = 1
+                elif encmode in ['dz', 'zz']:
+                    raise AssertionError("no encmode %s, use 'sz'" % encmode)
                 else:
                     raise AssertionError("unknown encmode %s" % encmode)
             else: