From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 8 Nov 2018 18:12:08 +0000 (+0000)
Subject: very bad hack on xlen=32 to sign-extend out into top bits of 64-bit register
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=076a2d2b17fdbceac2e0643689a69367caf78d92;p=riscv-isa-sim.git

very bad hack on xlen=32 to sign-extend out into top bits of 64-bit register
---

diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index dc3037c..b6312ad 100644
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -236,6 +236,14 @@ void (sv_proc_t::WRITE_REG)(reg_spec_t const& spec, sv_reg_t const& value)
                 report[0] = 'z';
             }
         }
+        // XXX BAD HACK, keep an eye on this
+        // when xlen = 32, spike appears to expect all 32-bit
+        // results to be sign-extended in the 64-bit register.
+        // this MAY not be properly spec-compliant when xlen
+        // is changed at runtime.
+        if (xlen == 32 && bitwidth != 32) {
+            wval = sext_bwid(wval, 32);
+        }
         fprintf(stderr, "writereg %s %ld bitwidth %d offs %d shift %d %lx " \
                         " %lx %lx %lx\n",
                         report, spec.reg, bitwidth, offs, shift, data,