From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 21 Aug 2019 03:37:52 +0000 (-0700)
Subject: Missing newline
X-Git-Tag: working-ls180~1120
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=076af2e6176ecc440be7b7fa984ea5b461bb95de;p=yosys.git

Missing newline
---

diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc
index 555de9fba..a176357a7 100644
--- a/techlibs/common/synth.cc
+++ b/techlibs/common/synth.cc
@@ -175,7 +175,7 @@ struct SynthPass : public ScriptPass
 			log_cmd_error("This command only operates on fully selected designs!\n");
 
 		if (abc == "abc9" && !lut)
-			log_cmd_error("ABC9 flow only supported for FPGA synthesis (using '-lut' option)");
+			log_cmd_error("ABC9 flow only supported for FPGA synthesis (using '-lut' option)\n");
 
 		log_header(design, "Executing SYNTH pass.\n");
 		log_push();