From: Marek Olšák Date: Sun, 1 Apr 2018 22:28:20 +0000 (-0400) Subject: radeonsi: rename a few R600/r600_ -> SI_/si_ X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=076afb4f0e71ece84b875466da920aa62415151a;p=mesa.git radeonsi: rename a few R600/r600_ -> SI_/si_ Acked-by: Timothy Arceri --- diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c index 9ae2a07343a..d2529971861 100644 --- a/src/gallium/drivers/radeonsi/si_clear.c +++ b/src/gallium/drivers/radeonsi/si_clear.c @@ -231,7 +231,7 @@ void vi_dcc_clear_level(struct si_context *sctx, } si_clear_buffer(sctx, dcc_buffer, dcc_offset, clear_size, - clear_value, R600_COHERENCY_CB_META); + clear_value, SI_COHERENCY_CB_META); } /* Set the same micro tile mode as the destination of the last MSAA resolve. @@ -461,7 +461,7 @@ static void si_do_fast_color_clear(struct si_context *sctx, si_clear_buffer(sctx, &tex->cmask_buffer->b.b, tex->cmask.offset, tex->cmask.size, - 0xCCCCCCCC, R600_COHERENCY_CB_META); + 0xCCCCCCCC, SI_COHERENCY_CB_META); need_decompress_pass = true; } @@ -493,7 +493,7 @@ static void si_do_fast_color_clear(struct si_context *sctx, /* Do the fast clear. */ si_clear_buffer(sctx, &tex->cmask_buffer->b.b, tex->cmask.offset, tex->cmask.size, 0, - R600_COHERENCY_CB_META); + SI_COHERENCY_CB_META); need_decompress_pass = true; } diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c b/src/gallium/drivers/radeonsi/si_cp_dma.c index 7ce931a1d24..ffdb78c3e40 100644 --- a/src/gallium/drivers/radeonsi/si_cp_dma.c +++ b/src/gallium/drivers/radeonsi/si_cp_dma.c @@ -61,7 +61,7 @@ static inline unsigned cp_dma_max_byte_count(struct si_context *sctx) */ static void si_emit_cp_dma(struct si_context *sctx, uint64_t dst_va, uint64_t src_va, unsigned size, unsigned flags, - enum r600_coherency coher) + enum si_coherency coher) { struct radeon_winsys_cs *cs = sctx->b.gfx_cs; uint32_t header = 0, command = 0; @@ -123,31 +123,31 @@ static void si_emit_cp_dma(struct si_context *sctx, uint64_t dst_va, * indices. If we wanted to execute CP DMA in PFP, this packet * should precede it. */ - if (coher == R600_COHERENCY_SHADER && flags & CP_DMA_SYNC) { + if (coher == SI_COHERENCY_SHADER && flags & CP_DMA_SYNC) { radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0)); radeon_emit(cs, 0); } } -static unsigned get_flush_flags(struct si_context *sctx, enum r600_coherency coher) +static unsigned get_flush_flags(struct si_context *sctx, enum si_coherency coher) { switch (coher) { default: - case R600_COHERENCY_NONE: + case SI_COHERENCY_NONE: return 0; - case R600_COHERENCY_SHADER: + case SI_COHERENCY_SHADER: return SI_CONTEXT_INV_SMEM_L1 | SI_CONTEXT_INV_VMEM_L1 | (sctx->b.chip_class == SI ? SI_CONTEXT_INV_GLOBAL_L2 : 0); - case R600_COHERENCY_CB_META: + case SI_COHERENCY_CB_META: return SI_CONTEXT_FLUSH_AND_INV_CB; } } -static unsigned get_tc_l2_flag(struct si_context *sctx, enum r600_coherency coher) +static unsigned get_tc_l2_flag(struct si_context *sctx, enum si_coherency coher) { - if ((sctx->b.chip_class >= GFX9 && coher == R600_COHERENCY_CB_META) || - (sctx->b.chip_class >= CIK && coher == R600_COHERENCY_SHADER)) + if ((sctx->b.chip_class >= GFX9 && coher == SI_COHERENCY_CB_META) || + (sctx->b.chip_class >= CIK && coher == SI_COHERENCY_SHADER)) return CP_DMA_USE_L2; return 0; @@ -206,7 +206,7 @@ static void si_cp_dma_prepare(struct si_context *sctx, struct pipe_resource *dst void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst, uint64_t offset, uint64_t size, unsigned value, - enum r600_coherency coher) + enum si_coherency coher) { struct radeon_winsys *ws = sctx->b.ws; struct r600_resource *rdst = r600_resource(dst); @@ -274,7 +274,7 @@ void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst, rdst->TC_L2_dirty = true; /* If it's not a framebuffer fast clear... */ - if (coher == R600_COHERENCY_SHADER) + if (coher == SI_COHERENCY_SHADER) sctx->b.num_cp_dma_calls++; } @@ -347,7 +347,7 @@ static void si_pipe_clear_buffer(struct pipe_context *ctx, } si_clear_buffer(sctx, dst, offset, size, dword_value, - R600_COHERENCY_SHADER); + SI_COHERENCY_SHADER); } /** @@ -388,7 +388,7 @@ static void si_cp_dma_realign_engine(struct si_context *sctx, unsigned size, va = sctx->scratch_buffer->gpu_address; si_emit_cp_dma(sctx, va, va + SI_CPDMA_ALIGNMENT, size, dma_flags, - R600_COHERENCY_SHADER); + SI_COHERENCY_SHADER); } /** @@ -404,8 +404,8 @@ void si_copy_buffer(struct si_context *sctx, uint64_t main_dst_offset, main_src_offset; unsigned skipped_size = 0; unsigned realign_size = 0; - unsigned tc_l2_flag = get_tc_l2_flag(sctx, R600_COHERENCY_SHADER); - unsigned flush_flags = get_flush_flags(sctx, R600_COHERENCY_SHADER); + unsigned tc_l2_flag = get_tc_l2_flag(sctx, SI_COHERENCY_SHADER); + unsigned flush_flags = get_flush_flags(sctx, SI_COHERENCY_SHADER); bool is_first = true; if (!size) @@ -462,7 +462,7 @@ void si_copy_buffer(struct si_context *sctx, user_flags, &is_first, &dma_flags); si_emit_cp_dma(sctx, main_dst_offset, main_src_offset, - byte_count, dma_flags, R600_COHERENCY_SHADER); + byte_count, dma_flags, SI_COHERENCY_SHADER); size -= byte_count; main_src_offset += byte_count; @@ -478,7 +478,7 @@ void si_copy_buffer(struct si_context *sctx, &is_first, &dma_flags); si_emit_cp_dma(sctx, dst_offset, src_offset, skipped_size, - dma_flags, R600_COHERENCY_SHADER); + dma_flags, SI_COHERENCY_SHADER); } /* Finally, realign the engine if the size wasn't aligned. */ diff --git a/src/gallium/drivers/radeonsi/si_gfx_cs.c b/src/gallium/drivers/radeonsi/si_gfx_cs.c index b54a2db2307..4340651b68f 100644 --- a/src/gallium/drivers/radeonsi/si_gfx_cs.c +++ b/src/gallium/drivers/radeonsi/si_gfx_cs.c @@ -83,7 +83,7 @@ void si_flush_gfx_cs(struct si_context *ctx, unsigned flags, if (ctx->screen->debug_flags & DBG(CHECK_VM)) flags &= ~PIPE_FLUSH_ASYNC; - /* If the state tracker is flushing the GFX IB, r600_flush_from_st is + /* If the state tracker is flushing the GFX IB, si_flush_from_st is * responsible for flushing the DMA IB and merging the fences from both. * This code is only needed when the driver flushes the GFX IB * internally, and it never asks for a fence handle. diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index 298391127dd..588e9255472 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -528,7 +528,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, /* Clear the NULL constant buffer, because loads should return zeros. */ si_clear_buffer(sctx, sctx->null_const_buf.buffer, 0, sctx->null_const_buf.buffer->width0, 0, - R600_COHERENCY_SHADER); + SI_COHERENCY_SHADER); } uint64_t max_threads_per_block; diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index edfc5fa2ed5..e726268aa0a 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -764,15 +764,15 @@ void si_init_clear_functions(struct si_context *sctx); SI_CPDMA_SKIP_GFX_SYNC | \ SI_CPDMA_SKIP_BO_LIST_UPDATE) -enum r600_coherency { - R600_COHERENCY_NONE, /* no cache flushes needed */ - R600_COHERENCY_SHADER, - R600_COHERENCY_CB_META, +enum si_coherency { + SI_COHERENCY_NONE, /* no cache flushes needed */ + SI_COHERENCY_SHADER, + SI_COHERENCY_CB_META, }; void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst, uint64_t offset, uint64_t size, unsigned value, - enum r600_coherency coher); + enum si_coherency coher); void si_copy_buffer(struct si_context *sctx, struct pipe_resource *dst, struct pipe_resource *src, uint64_t dst_offset, uint64_t src_offset, unsigned size, diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index d8261f106d7..bf39d4cd2e3 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -1407,7 +1407,7 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info) si_need_gfx_cs_space(sctx); - /* Since we've called r600_context_add_resource_size for vertex buffers, + /* Since we've called si_context_add_resource_size for vertex buffers, * this must be called after si_need_cs_space, because we must let * need_cs_space flush before we add buffers to the buffer list. */