From: Francisco Jerez Date: Thu, 23 Apr 2015 11:24:14 +0000 (+0300) Subject: i965: Add untyped surface write opcode. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0775d8835ac8d1f2ab75d04f0cddbad36b6787fe;p=mesa.git i965: Add untyped surface write opcode. Reviewed-by: Topi Pohjolainen Acked-by: Kenneth Graunke --- diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 4a4ff1d26d7..37494f892f4 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -904,6 +904,7 @@ enum opcode { SHADER_OPCODE_UNTYPED_ATOMIC, SHADER_OPCODE_UNTYPED_SURFACE_READ, + SHADER_OPCODE_UNTYPED_SURFACE_WRITE, SHADER_OPCODE_GEN4_SCRATCH_READ, SHADER_OPCODE_GEN4_SCRATCH_WRITE, diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h index 1d0e5634027..a1f4c536bc2 100644 --- a/src/mesa/drivers/dri/i965/brw_eu.h +++ b/src/mesa/drivers/dri/i965/brw_eu.h @@ -416,6 +416,13 @@ brw_untyped_surface_read(struct brw_codegen *p, unsigned msg_length, unsigned num_channels); +void +brw_untyped_surface_write(struct brw_codegen *p, + struct brw_reg payload, + struct brw_reg surface, + unsigned msg_length, + unsigned num_channels); + void brw_pixel_interpolator_query(struct brw_codegen *p, struct brw_reg dest, diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index 3ae1a1a56ac..cc45da17a93 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -2894,6 +2894,57 @@ brw_untyped_surface_read(struct brw_codegen *p, p, insn, num_channels); } +static void +brw_set_dp_untyped_surface_write_message(struct brw_codegen *p, + struct brw_inst *insn, + unsigned num_channels) +{ + const struct brw_device_info *devinfo = p->devinfo; + /* Set mask of 32-bit channels to drop. */ + unsigned msg_control = 0xf & (0xf << num_channels); + + if (brw_inst_access_mode(devinfo, p->current) == BRW_ALIGN_1) { + if (p->compressed) + msg_control |= 1 << 4; /* SIMD16 mode */ + else + msg_control |= 2 << 4; /* SIMD8 mode */ + } else { + if (devinfo->gen >= 8 || devinfo->is_haswell) + msg_control |= 0 << 4; /* SIMD4x2 mode */ + else + msg_control |= 2 << 4; /* SIMD8 mode */ + } + + brw_inst_set_dp_msg_type(devinfo, insn, + devinfo->gen >= 8 || devinfo->is_haswell ? + HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE : + GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE); + brw_inst_set_dp_msg_control(devinfo, insn, msg_control); +} + +void +brw_untyped_surface_write(struct brw_codegen *p, + struct brw_reg payload, + struct brw_reg surface, + unsigned msg_length, + unsigned num_channels) +{ + const struct brw_device_info *devinfo = p->devinfo; + const unsigned sfid = (devinfo->gen >= 8 || devinfo->is_haswell ? + HSW_SFID_DATAPORT_DATA_CACHE_1 : + GEN7_SFID_DATAPORT_DATA_CACHE); + const bool align1 = brw_inst_access_mode(devinfo, p->current) == BRW_ALIGN_1; + /* Mask out unused components -- See comment in brw_untyped_atomic(). */ + const unsigned mask = devinfo->gen == 7 && !devinfo->is_haswell && !align1 ? + WRITEMASK_X : WRITEMASK_XYZW; + struct brw_inst *insn = brw_send_indirect_surface_message( + p, sfid, brw_writemask(brw_null_reg(), mask), + payload, surface, msg_length, 0, align1); + + brw_set_dp_untyped_surface_write_message( + p, insn, num_channels); +} + void brw_pixel_interpolator_query(struct brw_codegen *p, struct brw_reg dest, diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index c0abff1ba0e..ec4c1a87fd2 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -502,6 +502,7 @@ fs_inst::is_send_from_grf() const case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET: case SHADER_OPCODE_UNTYPED_ATOMIC: case SHADER_OPCODE_UNTYPED_SURFACE_READ: + case SHADER_OPCODE_UNTYPED_SURFACE_WRITE: case SHADER_OPCODE_URB_WRITE_SIMD8: return true; case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD: @@ -956,6 +957,8 @@ fs_inst::regs_read(int arg) const return mlen; } else if (opcode == SHADER_OPCODE_UNTYPED_SURFACE_READ && arg == 0) { return mlen; + } else if (opcode == SHADER_OPCODE_UNTYPED_SURFACE_WRITE && arg == 0) { + return mlen; } else if (opcode == FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET && arg == 0) { return mlen; } else if (opcode == FS_OPCODE_LINTERP && arg == 0) { @@ -1048,6 +1051,7 @@ fs_visitor::implied_mrf_writes(fs_inst *inst) return 2; case SHADER_OPCODE_UNTYPED_ATOMIC: case SHADER_OPCODE_UNTYPED_SURFACE_READ: + case SHADER_OPCODE_UNTYPED_SURFACE_WRITE: case SHADER_OPCODE_URB_WRITE_SIMD8: case FS_OPCODE_INTERPOLATE_AT_CENTROID: case FS_OPCODE_INTERPOLATE_AT_SAMPLE: diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp index efe05e34ae4..7fe1afa6b32 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp @@ -2030,6 +2030,12 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width) brw_mark_surface_used(prog_data, src[1].dw1.ud); break; + case SHADER_OPCODE_UNTYPED_SURFACE_WRITE: + assert(src[2].file == BRW_IMMEDIATE_VALUE); + brw_untyped_surface_write(p, src[0], src[1], + inst->mlen, src[2].dw1.ud); + break; + case FS_OPCODE_SET_SIMD4X2_OFFSET: generate_set_simd4x2_offset(inst, dst, src[0]); break; diff --git a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp index a8bd93d7caa..a439399fe38 100644 --- a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp +++ b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp @@ -358,6 +358,7 @@ schedule_node::set_latency_gen7(bool is_haswell) break; case SHADER_OPCODE_UNTYPED_SURFACE_READ: + case SHADER_OPCODE_UNTYPED_SURFACE_WRITE: /* Test code: * mov(8) g112<1>UD 0x00000000UD { align1 WE_all 1Q }; * mov(1) g112.7<1>UD g1.7<0,1,0>UD { align1 WE_all }; diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp index 4fbd8d063e3..df09c226547 100644 --- a/src/mesa/drivers/dri/i965/brw_shader.cpp +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp @@ -494,6 +494,8 @@ brw_instruction_name(enum opcode op) return "untyped_atomic"; case SHADER_OPCODE_UNTYPED_SURFACE_READ: return "untyped_surface_read"; + case SHADER_OPCODE_UNTYPED_SURFACE_WRITE: + return "untyped_surface_write"; case SHADER_OPCODE_LOAD_PAYLOAD: return "load_payload"; @@ -1038,6 +1040,7 @@ backend_instruction::has_side_effects() const switch (opcode) { case SHADER_OPCODE_UNTYPED_ATOMIC: case SHADER_OPCODE_GEN4_SCRATCH_WRITE: + case SHADER_OPCODE_UNTYPED_SURFACE_WRITE: case SHADER_OPCODE_URB_WRITE_SIMD8: case FS_OPCODE_FB_WRITE: return true; diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp index 1160fdfdb54..31d8af305ff 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp @@ -216,6 +216,7 @@ vec4_instruction::is_send_from_grf() case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7: case SHADER_OPCODE_UNTYPED_ATOMIC: case SHADER_OPCODE_UNTYPED_SURFACE_READ: + case SHADER_OPCODE_UNTYPED_SURFACE_WRITE: return true; default: return false; @@ -232,6 +233,7 @@ vec4_instruction::regs_read(unsigned arg) const case SHADER_OPCODE_SHADER_TIME_ADD: case SHADER_OPCODE_UNTYPED_ATOMIC: case SHADER_OPCODE_UNTYPED_SURFACE_READ: + case SHADER_OPCODE_UNTYPED_SURFACE_WRITE: return arg == 0 ? mlen : 1; case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7: diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp index c6d98d584e8..f1fce1735c7 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp @@ -1484,6 +1484,12 @@ vec4_generator::generate_code(const cfg_t *cfg) brw_mark_surface_used(&prog_data->base, src[1].dw1.ud); break; + case SHADER_OPCODE_UNTYPED_SURFACE_WRITE: + assert(src[2].file == BRW_IMMEDIATE_VALUE); + brw_untyped_surface_write(p, src[0], src[1], inst->mlen, + src[2].dw1.ud); + break; + case VS_OPCODE_UNPACK_FLAGS_SIMD4X2: generate_unpack_flags(dst); break;