From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 14 Apr 2022 11:03:12 +0000 (+0100)
Subject: code-comments for when ASyncBridge is deployed
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=077d2a80336db3a52d7a81165c22deea5ed0d507;p=ls2.git

code-comments for when ASyncBridge is deployed
---

diff --git a/src/ls2.py b/src/ls2.py
index 045ea4b..4819cdc 100644
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -379,8 +379,11 @@ class DDR3SoC(SoC, Elaboratable):
             # HOWEVER, when the ASyncBridge is deployed, the two domains
             # must NOT be renamed, instead this used:
             #drs = lambda x: x
-            # and then the ASyncBridge takes care of it.
-            # but, back in ecp5_crg.py,
+            # and then the ASyncBridge takes care of the two.
+            # but, back in ecp5_crg.py, when ASyncBridge is added,
+            # dram_clk_freq must be passed to ECP5CRG, which will call
+            # ECP5CRG.phase2_domain on your behalf, setting up the
+            # necessary dramsync2x which is needed for the xdr=4 IOpads
 
             if fpga == 'sim':
                 self.ddrphy = FakePHY(module=ddrmodule,