From: whitequark Date: Fri, 14 Dec 2018 10:57:13 +0000 (+0000) Subject: back.pysim: robustly retrieve vcd names for clk/rst when writing gtkw. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=07814c0fee5f01c42d7081765d920de05cf3455b;p=nmigen.git back.pysim: robustly retrieve vcd names for clk/rst when writing gtkw. --- diff --git a/nmigen/back/pysim.py b/nmigen/back/pysim.py index c228611..6db3eaa 100644 --- a/nmigen/back/pysim.py +++ b/nmigen/back/pysim.py @@ -513,8 +513,8 @@ class Simulator: for domain, cd in self._domains.items(): with gtkw_save.group("d.{}".format(domain)): if cd.rst is not None: - gtkw_save.trace("top.{}".format(cd.rst.name)) - gtkw_save.trace("top.{}".format(cd.clk.name)) + gtkw_save.trace(self._vcd_names[cd.rst]) + gtkw_save.trace(self._vcd_names[cd.clk]) for signal in self._gtkw_signals: if signal in self._vcd_names: