From: Alberto Gonzalez <boqwxp@airmail.cc>
Date: Thu, 9 Apr 2020 05:34:28 +0000 (+0000)
Subject: Clean up `passes/cmds/scatter.cc`.
X-Git-Tag: working-ls180~624^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0787af947f92d9d1040623b5d2e8c737c0aee0a9;p=yosys.git

Clean up `passes/cmds/scatter.cc`.
---

diff --git a/passes/cmds/scatter.cc b/passes/cmds/scatter.cc
index 7123ba9fb..8c95e4289 100644
--- a/passes/cmds/scatter.cc
+++ b/passes/cmds/scatter.cc
@@ -46,22 +46,19 @@ struct ScatterPass : public Pass {
 		CellTypes ct(design);
 		extra_args(args, 1, design);
 
-		for (auto &mod_it : design->modules_)
+		for (auto module : design->selected_modules())
 		{
-			if (!design->selected(mod_it.second))
-				continue;
-
-			for (auto &c : mod_it.second->cells_)
-			for (auto &p : c.second->connections_)
+			for (auto cell : module->cells())
+			for (auto &p : cell->connections_)
 			{
-				RTLIL::Wire *wire = mod_it.second->addWire(NEW_ID, p.second.size());
+				RTLIL::Wire *wire = module->addWire(NEW_ID, p.second.size());
 
-				if (ct.cell_output(c.second->type, p.first)) {
+				if (ct.cell_output(cell->type, p.first)) {
 					RTLIL::SigSig sigsig(p.second, wire);
-					mod_it.second->connect(sigsig);
+					module->connect(sigsig);
 				} else {
 					RTLIL::SigSig sigsig(wire, p.second);
-					mod_it.second->connect(sigsig);
+					module->connect(sigsig);
 				}
 
 				p.second = wire;