From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 5 Feb 2014 00:59:30 +0000 (+0100)
Subject: Updated todo items in README file
X-Git-Tag: yosys-0.2.0~88
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=078cecf9eaa234b868ec3a30b281217a00418d61;p=yosys.git

Updated todo items in README file
---

diff --git a/README b/README
index ee5eb7979..385ee2c0a 100644
--- a/README
+++ b/README
@@ -308,8 +308,7 @@ Roadmap / Large-scale TODOs
    - Improve Xilinx FGPA synthesis (RAMB, CARRY4, SLR, etc.)
 
 - Implement SAT-based formal equivialence checker
-   - Rewrite freduce pass with input-cone analysis
-   - Write equiv pass, base hypothesis on input cones
+   - Write equiv pass based on hint-based register mapping
 
 - Re-implement Verilog frontend (far future)
    - cleaner (easier to use, harder to use wrong) AST format
@@ -323,6 +322,7 @@ Other Unsorted TODOs
 - Implement missing Verilog 2005 features:
 
   - Multi-dimensional arrays
+  - Support for real (float) const. expressions and parameters
   - ROM modeling using $readmemh/$readmemb in "initial" blocks
   - Ignore what needs to be ignored (e.g. drive and charge strengths)
   - Check standard vs. implementation to identify missing features