From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 28 Jun 2019 06:29:11 +0000 (+0100)
Subject: add comment
X-Git-Tag: convert-csv-opcode-to-binary~4369
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0790b3346f9b095432ce38c3e5b4fbbd48a00e6d;p=libreriscv.git

add comment
---

diff --git a/simple_v_extension/specification/sv.setvl.mdwn b/simple_v_extension/specification/sv.setvl.mdwn
index bc237bf5b..7c200b215 100644
--- a/simple_v_extension/specification/sv.setvl.mdwn
+++ b/simple_v_extension/specification/sv.setvl.mdwn
@@ -70,6 +70,16 @@ The encoding I (programmerjake) was planning on using is:
 
 It leaves space for future expansion to RV128 and/or multi-register predicates.
 
+> it's the opcode and funct7 that are actually used to determine the
+> instruction for almost all RISC-V instructions, therefore, I think we
+> should use the lower bits of the immediate in I-type to encode MAXVL.
+> This also has the benefit of simple extension of VL/MAXVL since the
+> bits immediately above the MAXVL field aren't used. If a new
+> instruction wants to be able to use rs2, it simply uses the encoding
+> with bit 31 set, which already indicates that rs2 is wanted in the V
+> extension.
+
+>> yep, good logic.
 
 # pseudocode