From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 24 Dec 2020 15:15:00 +0000 (+0000)
Subject: remove darn from svp64
X-Git-Tag: convert-csv-opcode-to-binary~949
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=07aab3d35a8031d8f2ad9cff373a5cfde1b3aed2;p=libreriscv.git

remove darn from svp64
---

diff --git a/openpower/opcode_regs_deduped.mdwn b/openpower/opcode_regs_deduped.mdwn
index cba32f80f..43087072f 100644
--- a/openpower/opcode_regs_deduped.mdwn
+++ b/openpower/opcode_regs_deduped.mdwn
@@ -317,7 +317,6 @@ major.csv | 11 | cmpi | D-Form |
 [[!table  data="""
 CSV | opcode | asm | form |
 minor_31.csv | 0b0010010000 | mtcrf/mtocrf | XFX-Form |
-minor_31.csv | 0b1011110011 | darn | X-Form |
 minor_63l.csv | 0b000000101 | 5/0=ftsqrt | -Form |
 minor_63l.csv | 0b011110110 | 22/7=mtfsf | -Form |
 """]]
@@ -668,10 +667,10 @@ ldcix | 2P | EXTRA2 | d:RT | s:RA | s:RB |  | RA_OR_ZERO | RB | NONE | RT | NONE
 
 [[!table  data="""
 insn | Ptype | Etype | 0 | 1 | 2 | 3 |
-stwu | 2P | EXTRA2 | d:RT | d:RA | s:RB |  | RA_OR_ZERO |  | RS | NONE | NONE | NONE |
-stbu | 2P | EXTRA2 | d:RT | d:RA | s:RB |  | RA_OR_ZERO |  | RS | NONE | NONE | NONE |
-sthu | 2P | EXTRA2 | d:RT | d:RA | s:RB |  | RA_OR_ZERO |  | RS | NONE | NONE | NONE |
-stdu | 2P | EXTRA2 | d:RT | d:RA | s:RB |  | RA_OR_ZERO |  | RS | NONE | NONE | NONE |
+stwu | 2P | EXTRA2 | d:RA | s:RS | s:RA |  | RA_OR_ZERO |  | RS | NONE | NONE | NONE |
+stbu | 2P | EXTRA2 | d:RA | s:RS | s:RA |  | RA_OR_ZERO |  | RS | NONE | NONE | NONE |
+sthu | 2P | EXTRA2 | d:RA | s:RS | s:RA |  | RA_OR_ZERO |  | RS | NONE | NONE | NONE |
+stdu | 2P | EXTRA2 | d:RA | s:RS | s:RA |  | RA_OR_ZERO |  | RS | NONE | NONE | NONE |
 """]]
 
 ## LDST-2R-2W (LDSTRM-2P-2S1D)
@@ -717,10 +716,10 @@ sthcx | 2P | EXTRA2 | s:RS,d:CR0 | s:RA | s:RB |  | RA_OR_ZERO | RB | RS | NONE
 
 [[!table  data="""
 insn | Ptype | Etype | 0 | 1 | 2 | 3 |
-stdux | 2P | EXTRA2 | d:RS | d:RA | s:RB |  | RA_OR_ZERO | RB | RS | NONE | NONE | NONE |
-stwux | 2P | EXTRA2 | d:RS | d:RA | s:RB |  | RA_OR_ZERO | RB | RS | NONE | NONE | NONE |
-stbux | 2P | EXTRA2 | d:RS | d:RA | s:RB |  | RA_OR_ZERO | RB | RS | NONE | NONE | NONE |
-sthux | 2P | EXTRA2 | d:RS | d:RA | s:RB |  | RA_OR_ZERO | RB | RS | NONE | NONE | NONE |
+stdux | 2P | EXTRA2 | d:RA | s:RS,s:RA | s:RB |  | RA_OR_ZERO | RB | RS | NONE | NONE | NONE |
+stwux | 2P | EXTRA2 | d:RA | s:RS,s:RA | s:RB |  | RA_OR_ZERO | RB | RS | NONE | NONE | NONE |
+stbux | 2P | EXTRA2 | d:RA | s:RS,s:RA | s:RB |  | RA_OR_ZERO | RB | RS | NONE | NONE | NONE |
+sthux | 2P | EXTRA2 | d:RA | s:RS,s:RA | s:RB |  | RA_OR_ZERO | RB | RS | NONE | NONE | NONE |
 """]]
 
 ## CRio (RM-2P-1S1D)
@@ -769,7 +768,6 @@ cmpi | 2P | EXTRA3 | d:BF | s:RA |  |  | RA |  | NONE | NONE | NONE | BF |
 [[!table  data="""
 insn | Ptype | Etype | 0 | 1 | 2 | 3 |
 mtcrf/mtocrf | 2P | EXTRA2 | d:CR | s:RS | s:CR |  | RS | NONE | NONE | NONE | WHOLE_REG | WHOLE_REG |
-darn | 2P | EXTRA2 | TODO |  |  |  |  |  | RT |  |  |  |
 5/0=ftsqrt | 2P | EXTRA2 | TODO |  |  |  | NONE | FRB | NONE | NONE | 0 | 1 |
 22/7=mtfsf | 2P | EXTRA2 | TODO |  |  |  | NONE | FRB | NONE | NONE | 0 | 0 |
 """]]
diff --git a/openpower/sv_analysis.py b/openpower/sv_analysis.py
index cb14228bf..395ad05ad 100644
--- a/openpower/sv_analysis.py
+++ b/openpower/sv_analysis.py
@@ -382,13 +382,13 @@ def process_csvs():
             elif value == 'LDSTRM-2P-2S1D':
                 if 'st' in insn_name and 'x' not in insn_name: # stwu/stbu etc
                     res['Etype'] = 'EXTRA2' # RM EXTRA2 type
-                    res['0'] = 'd:RS' # RS: Rdest1_EXTRA2
-                    res['1'] = 'd:RA' # RA: Rdest2_EXTRA2
-                    res['2'] = 's:RA' # RA: Rsrc1_EXTRA2
-                if 'st' in insn_name and 'x' in insn_name: # stwux
+                    res['0'] = 'd:RA' # RA: Rdest1_EXTRA2
+                    res['1'] = 's:RS' # RS: Rdsrc1_EXTRA2
+                    res['2'] = 's:RA' # RA: Rsrc2_EXTRA2
+                elif 'st' in insn_name and 'x' in insn_name: # stwux
                     res['Etype'] = 'EXTRA2' # RM EXTRA2 type
-                    res['0'] = 'd:RS' # RS: Rdest1_EXTRA2
-                    res['1'] = 'd:RA' # RA: Rdest2_EXTRA2, RA: Rsrc1_EXTRA2
+                    res['0'] = 'd:RA' # RA: Rdest1_EXTRA2
+                    res['1'] = 's:RS,s:RA' # RS: Rdest2_EXTRA2, RA: Rsrc1_EXTRA2
                     res['2'] = 's:RB' # RB: Rsrc2_EXTRA2
                 elif 'u' in insn_name: # ldux etc.
                     res['Etype'] = 'EXTRA2' # RM EXTRA2 type