From: Luke Kenneth Casson Leighton Date: Thu, 1 Oct 2020 17:10:26 +0000 (+0100) Subject: add clksel, pll to ls180 X-Git-Tag: 24jan2021_ls180~262 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=07bea73b0e1695a0d66ada3c3526baaf365608c7;p=soc.git add clksel, pll to ls180 --- diff --git a/src/soc/litex/florent/libresoc/core.py b/src/soc/litex/florent/libresoc/core.py index 9cc7d893..15c1c9f6 100644 --- a/src/soc/litex/florent/libresoc/core.py +++ b/src/soc/litex/florent/libresoc/core.py @@ -194,6 +194,13 @@ class LibreSoC(CPU): o_dmi_ack_o = self.dmi_ack, )) + # add clock select, pll output + if variant == "ls180": + self.pll_48_o = Signal() + self.clk_sel = Signal(3) + self.cpu_params['i_clk_sel_i'] = self.clk_sel + self.cpu_params['o_pll_48_o'] = self.pll_48_o + # add wishbone buses to cpu params self.cpu_params.update(make_wb_bus("ibus", ibus)) self.cpu_params.update(make_wb_bus("dbus", dbus)) diff --git a/src/soc/litex/florent/libresoc/ls180.py b/src/soc/litex/florent/libresoc/ls180.py index 6e122c66..8d32a907 100644 --- a/src/soc/litex/florent/libresoc/ls180.py +++ b/src/soc/litex/florent/libresoc/ls180.py @@ -24,110 +24,115 @@ from libresoc.ls180io import make_uart, make_gpio import os -# IOs ---------------------------------------------------------------------------------------------- - -_io = [ - # CLK/RST: 2 pins - ("sys_clk", 0, Pins("G2"), IOStandard("LVCMOS33")), - ("sys_rst", 0, Pins("R1"), IOStandard("LVCMOS33")), - - # JTAG0: 4 pins - ("jtag", 0, - Subsignal("tms", Pins("Z1"), IOStandard("LVCMOS33")), - Subsignal("tck", Pins("Z2"), IOStandard("LVCMOS33")), - Subsignal("tdi", Pins("Z3"), IOStandard("LVCMOS33")), - Subsignal("tdo", Pins("Z4"), IOStandard("LVCMOS33")), - ), - - # I2C0: 2 pins - ("i2c", 0, - Subsignal("scl", Pins("L4"), IOStandard("LVCMOS33")), - Subsignal("sda_i", Pins("M1"), IOStandard("LVCMOS33")), - Subsignal("sda_o", Pins("M1"), IOStandard("LVCMOS33")), - Subsignal("sda_oe", Pins("M1"), IOStandard("LVCMOS33")), - ), - - # SPI0: 4 pins - ("spi_master", 0, - Subsignal("clk", Pins("J1")), - Subsignal("mosi", Pins("J3"), Misc("PULLMODE=UP")), - Subsignal("cs_n", Pins("H1"), Misc("PULLMODE=UP")), - Subsignal("miso", Pins("K2"), Misc("PULLMODE=UP")), - Misc("SLEWRATE=FAST"), - IOStandard("LVCMOS33"), - ), - - # SPICARD0: 4 pins - ("spisdcard", 0, - Subsignal("clk", Pins("J1")), - Subsignal("mosi", Pins("J3"), Misc("PULLMODE=UP")), - Subsignal("cs_n", Pins("H1"), Misc("PULLMODE=UP")), - Subsignal("miso", Pins("K2"), Misc("PULLMODE=UP")), - Misc("SLEWRATE=FAST"), - IOStandard("LVCMOS33"), - ), - - # SDCARD0: 6 pins - ("sdcard", 0, - Subsignal("clk", Pins("J1")), - Subsignal("cmd_i", Pins("J3"), Misc("PULLMODE=UP")), - Subsignal("cmd_o", Pins("J3"), Misc("PULLMODE=UP")), - Subsignal("cmd_oe", Pins("J3"), Misc("PULLMODE=UP")), - Subsignal("data_i", Pins("K2 K1 H2 H1"), Misc("PULLMODE=UP")), - Subsignal("data_o", Pins("K2 K1 H2 H1"), Misc("PULLMODE=UP")), - Subsignal("data_oe", Pins("K2"), Misc("PULLMODE=UP")), - Misc("SLEWRATE=FAST"), - IOStandard("LVCMOS33"), - ), - - # SDRAM: 39 pins - ("sdram_clock", 0, Pins("F19"), IOStandard("LVCMOS33")), - ("sdram", 0, - Subsignal("a", Pins( - "M20 M19 L20 L19 K20 K19 K18 J20", - "J19 H20 N19 G20 G19")), - Subsignal("dq_i", Pins( - "J16 L18 M18 N18 P18 T18 T17 U20", - "E19 D20 D19 C20 E18 F18 J18 J17")), - Subsignal("dq_o", Pins( - "J16 L18 M18 N18 P18 T18 T17 U20", - "E19 D20 D19 C20 E18 F18 J18 J17")), - Subsignal("dq_oe", Pins("J17")), - Subsignal("we_n", Pins("T20")), - Subsignal("ras_n", Pins("R20")), - Subsignal("cas_n", Pins("T19")), - Subsignal("cs_n", Pins("P30")), - Subsignal("cke", Pins("F21")), - Subsignal("ba", Pins("P19 N20")), - Subsignal("dm", Pins("U19 E20")), - IOStandard("LVCMOS33"), - Misc("SLEWRATE=FAST"), - ), - - # PWM: 2 pins - ("pwm", 0, Pins("P1"), IOStandard("LVCMOS33")), - ("pwm", 1, Pins("P2"), IOStandard("LVCMOS33")), -] - -n_gpio = 16 - -# 16 GPIOs -_io.append( make_gpio("gpio", 0, n_gpio) ) - -# EINT: 3 pins -_io.append( ("eint", 0, Pins("E0 E1 E2"), IOStandard("LVCMOS33")) ) - -# UART0: 2 pins -_io.append(make_uart("uart", 0)) -# UART1: 2 pins -_io.append(make_uart("uart", 1)) - -# not connected - eurgh have to adjust this to match the total pincount. -num_nc = 40 -nc = ' '.join("NC%d" % i for i in range(num_nc)) -_io.append(("nc", 0, Pins(nc), IOStandard("LVCMOS33"))) - -# Platform ----------------------------------------------------------------------------------------- +# IOs --------------------------------------------------------------------- + +def io(): + _io = [ + # CLK/RST: 2 pins + ("sys_clk", 0, Pins("G2"), IOStandard("LVCMOS33")), + ("sys_rst", 0, Pins("R1"), IOStandard("LVCMOS33")), + ("sys_clksel_i", 0, Pins("R1 R2 R3"), IOStandard("LVCMOS33")), + ("sys_pll_48_o", 0, Pins("R1"), IOStandard("LVCMOS33")), + + # JTAG0: 4 pins + ("jtag", 0, + Subsignal("tms", Pins("Z1"), IOStandard("LVCMOS33")), + Subsignal("tck", Pins("Z2"), IOStandard("LVCMOS33")), + Subsignal("tdi", Pins("Z3"), IOStandard("LVCMOS33")), + Subsignal("tdo", Pins("Z4"), IOStandard("LVCMOS33")), + ), + + # I2C0: 2 pins + ("i2c", 0, + Subsignal("scl", Pins("L4"), IOStandard("LVCMOS33")), + Subsignal("sda_i", Pins("M1"), IOStandard("LVCMOS33")), + Subsignal("sda_o", Pins("M1"), IOStandard("LVCMOS33")), + Subsignal("sda_oe", Pins("M1"), IOStandard("LVCMOS33")), + ), + + # SPI0: 4 pins + ("spi_master", 0, + Subsignal("clk", Pins("J1")), + Subsignal("mosi", Pins("J3"), Misc("PULLMODE=UP")), + Subsignal("cs_n", Pins("H1"), Misc("PULLMODE=UP")), + Subsignal("miso", Pins("K2"), Misc("PULLMODE=UP")), + Misc("SLEWRATE=FAST"), + IOStandard("LVCMOS33"), + ), + + # SPICARD0: 4 pins + ("spisdcard", 0, + Subsignal("clk", Pins("J1")), + Subsignal("mosi", Pins("J3"), Misc("PULLMODE=UP")), + Subsignal("cs_n", Pins("H1"), Misc("PULLMODE=UP")), + Subsignal("miso", Pins("K2"), Misc("PULLMODE=UP")), + Misc("SLEWRATE=FAST"), + IOStandard("LVCMOS33"), + ), + + # SDCARD0: 6 pins + ("sdcard", 0, + Subsignal("clk", Pins("J1")), + Subsignal("cmd_i", Pins("J3"), Misc("PULLMODE=UP")), + Subsignal("cmd_o", Pins("J3"), Misc("PULLMODE=UP")), + Subsignal("cmd_oe", Pins("J3"), Misc("PULLMODE=UP")), + Subsignal("data_i", Pins("K2 K1 H2 H1"), Misc("PULLMODE=UP")), + Subsignal("data_o", Pins("K2 K1 H2 H1"), Misc("PULLMODE=UP")), + Subsignal("data_oe", Pins("K2"), Misc("PULLMODE=UP")), + Misc("SLEWRATE=FAST"), + IOStandard("LVCMOS33"), + ), + + # SDRAM: 39 pins + ("sdram_clock", 0, Pins("F19"), IOStandard("LVCMOS33")), + ("sdram", 0, + Subsignal("a", Pins( + "M20 M19 L20 L19 K20 K19 K18 J20", + "J19 H20 N19 G20 G19")), + Subsignal("dq_i", Pins( + "J16 L18 M18 N18 P18 T18 T17 U20", + "E19 D20 D19 C20 E18 F18 J18 J17")), + Subsignal("dq_o", Pins( + "J16 L18 M18 N18 P18 T18 T17 U20", + "E19 D20 D19 C20 E18 F18 J18 J17")), + Subsignal("dq_oe", Pins("J17")), + Subsignal("we_n", Pins("T20")), + Subsignal("ras_n", Pins("R20")), + Subsignal("cas_n", Pins("T19")), + Subsignal("cs_n", Pins("P30")), + Subsignal("cke", Pins("F21")), + Subsignal("ba", Pins("P19 N20")), + Subsignal("dm", Pins("U19 E20")), + IOStandard("LVCMOS33"), + Misc("SLEWRATE=FAST"), + ), + + # PWM: 2 pins + ("pwm", 0, Pins("P1"), IOStandard("LVCMOS33")), + ("pwm", 1, Pins("P2"), IOStandard("LVCMOS33")), + ] + + n_gpio = 16 + + # 16 GPIOs + _io.append( make_gpio("gpio", 0, n_gpio) ) + + # EINT: 3 pins + _io.append( ("eint", 0, Pins("E0 E1 E2"), IOStandard("LVCMOS33")) ) + + # UART0: 2 pins + _io.append(make_uart("uart", 0)) + # UART1: 2 pins + _io.append(make_uart("uart", 1)) + + # not connected - eurgh have to adjust this to match the total pincount. + num_nc = 36 + nc = ' '.join("NC%d" % i for i in range(num_nc)) + _io.append(("nc", 0, Pins(nc), IOStandard("LVCMOS33"))) + + return _io + +# Platform ---------------------------------------------------------------- class LS180Platform(GenericPlatform): default_clk_name = "sys_clk" @@ -135,7 +140,7 @@ class LS180Platform(GenericPlatform): def __init__(self, device="LS180", **kwargs): assert device in ["LS180"] - GenericPlatform.__init__(self, device, _io, **kwargs) + GenericPlatform.__init__(self, device, io(), **kwargs) def build(self, fragment, build_dir = "build", diff --git a/src/soc/litex/florent/ls180soc.py b/src/soc/litex/florent/ls180soc.py index ecb10bcc..860f8203 100755 --- a/src/soc/litex/florent/ls180soc.py +++ b/src/soc/litex/florent/ls180soc.py @@ -363,6 +363,13 @@ class LibreSoCSim(SoCCore): self.submodules.crg = CRG(platform.request("sys_clk"), platform.request("sys_rst")) + # PLL/Clock Select + clksel_i = platform.request("sys_clksel_i") + pll48_o = platform.request("sys_pll_48_o") + + self.comb += self.cpu.clk_sel.eq(clksel_i) # allow clock src select + self.comb += pll48_o.eq(self.cpu.pll_48_o) # "test feed" from the PLL + #ram_init = [] # SDRAM ---------------------------------------------------- diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index 61a4f2bc..10696d79 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -468,6 +468,7 @@ class TestIssuer(Elaboratable): comb += cd_pll.clk.eq(pll.clk_pll_o) # wire up external 24mhz to PLL and clksel + comb += clksel.clk_24_i.eq(ClockSignal()) comb += pll.clk_24_i.eq(clksel.clk_24_i) # now wire up ResetSignals. don't mind them all being in this domain