From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 15 Oct 2020 20:43:22 +0000 (+0100)
Subject: add commented-out connection to JTAG in ECP5 litex
X-Git-Tag: 24jan2021_ls180~144
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=07db89fcd0597d852ea28f4787451b840a7e1a2a;p=soc.git

add commented-out connection to JTAG in ECP5 litex
---

diff --git a/src/soc/litex/florent/versa_ecp5.py b/src/soc/litex/florent/versa_ecp5.py
index bd565b0b..8774b849 100755
--- a/src/soc/litex/florent/versa_ecp5.py
+++ b/src/soc/litex/florent/versa_ecp5.py
@@ -34,6 +34,21 @@ class VersaECP5TestSoC(versa_ecp5.BaseSoC):
             device       = "LFE5UM",
             **kwargs)
 
+        if False: # well that didn't work.  connectors are different
+                  # from platform IO.
+            # get 4 arbitrarily-selected pins from the X3 connector
+            jtag_tck = self.platform.request("X3", "B19")
+            jtag_tms = self.platform.request("X3", "B12")
+            jtag_tdi = self.platform.request("X3", "B9")
+            jtag_tdo = self.platform.request("X3", "E6")
+
+            # wire the pins up to CPU JTAG
+            self.comb += self.cpu.jtag_tck.eq(jtag_tck)
+            self.comb += self.cpu.jtag_tms.eq(jtag_tms)
+            self.comb += self.cpu.jtag_tdi.eq(jtag_tdi)
+            self.comb += jtag_tdo.eq(self.cpu.jtag_tdo)
+
+
         #self.add_constant("MEMTEST_BUS_SIZE",  256//16)
         #self.add_constant("MEMTEST_DATA_SIZE", 256//16)
         #self.add_constant("MEMTEST_ADDR_SIZE", 256//16)