From: Kevin Lim <ktlim@umich.edu>
Date: Sun, 26 Nov 2006 16:46:58 +0000 (-0500)
Subject: Include check for making sure caches are enabled.
X-Git-Tag: m5_2.0_beta2~17
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=07e525e8b78fba0ebaf5c50f32fbf30d17051891;p=gem5.git

Include check for making sure caches are enabled.

--HG--
extra : convert_revision : e3902b065db524ebe5bf762e44a840133ccb8d75
---

diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py
index 374ff3fc2..e037d0343 100644
--- a/configs/common/Simulation.py
+++ b/configs/common/Simulation.py
@@ -39,6 +39,9 @@ def setCPUClass(options):
     if options.timing:
         TmpClass = TimingSimpleCPU
     elif options.detailed:
+        if not options.caches:
+            print "O3 CPU must be used with caches"
+            sys.exit(1)
         TmpClass = DerivO3CPU
     else:
         TmpClass = AtomicSimpleCPU