From: Shriya Sharma <shriya@redsemiconductor.com>
Date: Wed, 22 Nov 2023 14:03:58 +0000 (+0000)
Subject: Added English language description for addg6s instruction
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=07e8ea03e48915c37cd7d4b1e4daa5a47e113d12;p=openpower-isa.git

Added English language description for addg6s instruction
---

diff --git a/openpower/isa/bcd.mdwn b/openpower/isa/bcd.mdwn
index 81b96158..20e1fc24 100644
--- a/openpower/isa/bcd.mdwn
+++ b/openpower/isa/bcd.mdwn
@@ -51,6 +51,20 @@ Pseudo-code:
     nibbles_need_sixes <- ¬carries[0:XLEN-1] & ones
     RT <- nibbles_need_sixes * 0b0110
 
+Description:
+
+    The contents of register RA are added to the contents
+    of register RB. Sixteen carry bits are produced, one
+    for each carry out of decimal position n (bit posi-
+    tion 4xn).
+
+    A doubleword is composed from the 16 carry bits, and
+    placed into RT. The doubleword consists of a decimal
+    six (0b0110) in every decimal digit position for which
+    the corresponding carry bit is 0, and a zero (0b0000) in
+    every position for which the corresponding carry bit is
+    1.
+
 Special Registers Altered:
 
     None