From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 30 May 2019 18:32:14 +0000 (-0700)
Subject: Do not double count LUT1s
X-Git-Tag: working-ls180~1208^2~235
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0800846e73b6502cfaa2000ea433faa5f1f75a3a;p=yosys.git

Do not double count LUT1s
---

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 8966b5c27..b1bd167a4 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -670,7 +670,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 									RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset),
 									driver_lut);
 						}
-						cell_stats["$lut"]++;
 					}
 					else {
 						cell = module->addCell(remap_name(c->name), "$_NOT_");