From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Wed, 26 Jun 2013 20:45:47 +0000 (+0200)
Subject: fhdl/verilog: fix signedness rules for comparison
X-Git-Tag: 24jan2021_ls180~2099^2~549
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=080afdc3f9db811d7b53dd0da33d122219c594fd;p=litex.git

fhdl/verilog: fix signedness rules for comparison
---

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index 8dc404fe..d9683e94 100644
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -51,7 +51,7 @@ def _printexpr(ns, node):
 				s = s1
 		elif arity == 2:
 			r2, s2 = _printexpr(ns, node.operands[1])
-			if node.op in ["+", "-", "*", "&", "^", "|"]:
+			if node.op not in ["<<<", ">>>"]:
 				if s2 and not s1:
 					r1 = "$signed({1'd0, " + r1 + "})"
 				if s1 and not s2: