From: Rupert Swarbrick <rswarbrick@gmail.com>
Date: Mon, 20 Apr 2020 14:58:30 +0000 (+0100)
Subject: Simplify some RTLIL destructors
X-Git-Tag: yosys-0.10~139
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=081111714eed9cbc3dacac766cad85de30e98073;p=yosys.git

Simplify some RTLIL destructors

No change in behaviour, but use range-based for loops instead of
iterators.
---

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index a756218f3..b7bef723f 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -571,8 +571,8 @@ RTLIL::Design::Design()
 
 RTLIL::Design::~Design()
 {
-	for (auto it = modules_.begin(); it != modules_.end(); ++it)
-		delete it->second;
+	for (auto &pr : modules_)
+		delete pr.second;
 	for (auto n : verilog_packages)
 		delete n;
 	for (auto n : verilog_globals)
@@ -864,14 +864,14 @@ RTLIL::Module::Module()
 
 RTLIL::Module::~Module()
 {
-	for (auto it = wires_.begin(); it != wires_.end(); ++it)
-		delete it->second;
-	for (auto it = memories.begin(); it != memories.end(); ++it)
-		delete it->second;
-	for (auto it = cells_.begin(); it != cells_.end(); ++it)
-		delete it->second;
-	for (auto it = processes.begin(); it != processes.end(); ++it)
-		delete it->second;
+	for (auto &pr : wires_)
+		delete pr.second;
+	for (auto &pr : memories)
+		delete pr.second;
+	for (auto &pr : cells_)
+		delete pr.second;
+	for (auto &pr : processes)
+		delete pr.second;
 #ifdef WITH_PYTHON
 	RTLIL::Module::get_all_modules()->erase(hashidx_);
 #endif