From: lkcl <lkcl@web>
Date: Wed, 15 Sep 2021 17:15:27 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~117
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=081c3400482befdb2ce8ac64f2b26c6732f55c41;p=libreriscv.git

---

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index ffa1b2e95..e5e077015 100644
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -185,8 +185,9 @@ Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or in
 # Mode
 
 Mode is an augmentation of SV behaviour.  Different types of
-instructions have different needs, similar to Power ISA 64 bit prefix
-8LS and MTRR formats.
+instructions have different needs, similar to Power ISA 
+v3.1 64 bit prefix 8LS and MTRR formats apply to different
+instruction types
 
 * For condition register operations see [[sv/cr_ops]]
 * For LD/ST Modes, see [[sv/ldst]].