From: Kenneth Graunke <kenneth@whitecape.org>
Date: Fri, 26 Aug 2016 20:01:13 +0000 (-0700)
Subject: isl: Finish tiling filtering for Gen6.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=081f21f29bd6bee866ddb21d423ffa0506dd7bac;p=mesa.git

isl: Finish tiling filtering for Gen6.

Gen6 only has one additional restriction over Gen7+, so we just add it
to the existing gen7 function (which actually covers later gens too).

This should stop FINISHME spew when running GL on Sandybridge.

v2: Fix bytes per block vs. bits per block confusion (Jason) and
    rename function to gen6_filter_tiling (Jason and Chad).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
---

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index a883aecddb4..b6e88ad03e6 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -236,11 +236,11 @@ isl_surf_choose_tiling(const struct isl_device *dev,
 {
    isl_tiling_flags_t tiling_flags = info->tiling_flags;
 
-   if (ISL_DEV_GEN(dev) >= 7) {
-      gen7_filter_tiling(dev, info, &tiling_flags);
+   if (ISL_DEV_GEN(dev) >= 6) {
+      gen6_filter_tiling(dev, info, &tiling_flags);
    } else {
       isl_finishme("%s: gen%u", __func__, ISL_DEV_GEN(dev));
-      gen7_filter_tiling(dev, info, &tiling_flags);
+      gen6_filter_tiling(dev, info, &tiling_flags);
    }
 
    #define CHOOSE(__tiling) \
diff --git a/src/intel/isl/isl_gen7.c b/src/intel/isl/isl_gen7.c
index f3d8428d059..4f1cc9d5f1a 100644
--- a/src/intel/isl/isl_gen7.c
+++ b/src/intel/isl/isl_gen7.c
@@ -198,7 +198,7 @@ gen7_format_needs_valign2(const struct isl_device *dev,
  * flags except ISL_TILING_X_BIT and ISL_TILING_LINEAR_BIT.
  */
 void
-gen7_filter_tiling(const struct isl_device *dev,
+gen6_filter_tiling(const struct isl_device *dev,
                    const struct isl_surf_init_info *restrict info,
                    isl_tiling_flags_t *flags)
 {
@@ -297,6 +297,16 @@ gen7_filter_tiling(const struct isl_device *dev,
        */
       *flags &= ~ISL_TILING_Y0_BIT;
    }
+
+   /* From the Sandybridge PRM, Volume 1, Part 2, page 32:
+    *
+    *    "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either
+    *     TileX or Linear."
+    *
+    * This is necessary all the way back to 965, but is permitted on Gen7+.
+    */
+   if (ISL_DEV_GEN(dev) < 7 && isl_format_get_layout(info->format)->bpb >= 128)
+      *flags &= ~ISL_TILING_Y0_BIT;
 }
 
 /**
diff --git a/src/intel/isl/isl_gen7.h b/src/intel/isl/isl_gen7.h
index 5d19812092a..e35e2df4c4f 100644
--- a/src/intel/isl/isl_gen7.h
+++ b/src/intel/isl/isl_gen7.h
@@ -30,7 +30,7 @@ extern "C" {
 #endif
 
 void
-gen7_filter_tiling(const struct isl_device *dev,
+gen6_filter_tiling(const struct isl_device *dev,
                    const struct isl_surf_init_info *restrict info,
                    isl_tiling_flags_t *flags);