From: lkcl <lkcl@web>
Date: Fri, 17 Jun 2022 09:29:55 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1739
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=081ff62e316db59fe4b3557b0b9e40a420a6779c;p=libreriscv.git

---

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index baa34f319..cf169f446 100644
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -12,10 +12,10 @@ Obligatory Dilbert:
 
 <https://bugs.libre-soc.org/show_bug.cgi?id=213>
 
-SV is designed as a Vector ISA for Hybrid 3D CPU GPU VPU workloads.
+SV is designed as a Scalable Vector ISA for Hybrid 3D CPU GPU VPU workloads.
 As such it brings features normally only found in Cray Supercomputers
 (Cray-1, NEC SX-Aurora)
-and in GPUs, but keeps strictly to a *Simple* principle of leveraging
+and in GPUs, but keeps strictly to a *Simple* RISC principle of leveraging
 a *Scalar* ISA, exclusively using "Prefixing". **Not one single actual
 explicit Vector opcode exists in SV, at all**.
 
@@ -250,6 +250,33 @@ of a Vector Processor. Transcendentals can be added as a sub-RFC.
 
 ---
 
+SIMD ISAs commonly mistaken for Vector:
+---------------------------------------
+
+There is considerable confusion surrounding Vector ISAs
+because of a mis-use of the word "Vector" in most
+well-known Packed SIMD ISAs.
+
+* PackedSIMD VSX. VSX, which has the word "Vector" in its name,
+  is "inspired" by Vector Processing
+  but has no "Scaling" capability, and no Predicate masking
+* [AVX / AVX2 / AVX128 / AVX256 / AVX512](https://en.wikipedia.org/wiki/Advanced_Vector_Extensions)
+  again has the word "Vector" in its name but this in no
+  way makes it a Vector ISA. None of the AVX-\* family
+  are "Scalable" however there is at least Predicate Masking
+  in AVX-512.
+* ARM NEON - accurately described as a Packed SIMD ISA in
+  all literature.
+* ARM SVE / SVE2 - accurately described as a Scalable Vector
+  ISA, but the "Scaling" is, rather unfortunately, a parameter
+  that is chosen by the *Hardware Architect*, rather than
+  the programmer. This has resulted in programmers writing
+  multiple variants of hand-coded assembler in order
+  to target different machines with different hardware widths,
+  going directly against the advice given on ARM's developer
+  documentation.
+
+
 Actual 3D GPU Architectures and ISAs:
 -------------------------------------
 
@@ -268,8 +295,8 @@ Actual 3D GPU Architectures and ISAs:
   <https://miaowgpu.org/>
 
 
-Actual Vector Processor Architectures and ISAs:
------------------------------------------------
+Actual Scalar Vector Processor Architectures and ISAs:
+------------------------------------------------------
 
 * NEC SX Aurora
   <https://www.hpc.nec/documents/guide/pdfs/Aurora_ISA_guide.pdf>