From: Daniel Schürmann Date: Thu, 5 Dec 2019 17:32:52 +0000 (+0100) Subject: aco: use soffset for MUBUF instructions on SI/CI X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=08374714638fc477a783417b168f3d99ff7ca1b6;p=mesa.git aco: use soffset for MUBUF instructions on SI/CI pipeline-db changes for GFX7: 80310 shaders in 40472 tests Totals: SGPRS: 3655300 -> 3655900 (0.02 %) VGPRS: 2677732 -> 2678324 (0.02 %) Spilled SGPRs: 1730 -> 1730 (0.00 %) Spilled VGPRs: 14 -> 14 (0.00 %) Scratch size: 15540 -> 15540 (0.00 %) dwords per thread Code Size: 136488364 -> 136106120 (-0.28 %) bytes LDS: 1259 -> 1259 (0.00 %) blocks Max Waves: 601039 -> 601014 (-0.00 %) Totals from affected shaders: SGPRS: 316312 -> 316912 (0.19 %) VGPRS: 273844 -> 274436 (0.22 %) Spilled SGPRs: 770 -> 770 (0.00 %) Spilled VGPRs: 14 -> 14 (0.00 %) Scratch size: 16 -> 16 (0.00 %) dwords per thread Code Size: 22724904 -> 22342660 (-1.68 %) bytes LDS: 114 -> 114 (0.00 %) blocks Max Waves: 30861 -> 30836 (-0.08 %) Reviewed-by: Rhys Perry --- diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index 2c386b50a14..1cff595659c 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -3375,9 +3375,6 @@ void load_buffer(isel_context *ctx, unsigned num_components, Temp dst, aco_opcode op; if (dst.type() == RegType::vgpr || (ctx->options->chip_class < GFX8 && !readonly)) { - if (ctx->options->chip_class < GFX8) - offset = as_vgpr(ctx, offset); - Operand vaddr = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1); Operand soffset = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0); unsigned const_offset = 0; @@ -4469,12 +4466,7 @@ void visit_store_ssbo(isel_context *ctx, nir_intrinsic_instr *instr) Temp data = get_ssa_temp(ctx, instr->src[0].ssa); unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8; unsigned writemask = nir_intrinsic_write_mask(instr); - - Temp offset; - if (ctx->options->chip_class < GFX8) - offset = as_vgpr(ctx,get_ssa_temp(ctx, instr->src[2].ssa)); - else - offset = get_ssa_temp(ctx, instr->src[2].ssa); + Temp offset = get_ssa_temp(ctx, instr->src[2].ssa); Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[1].ssa)); rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u)); @@ -4611,12 +4603,7 @@ void visit_atomic_ssbo(isel_context *ctx, nir_intrinsic_instr *instr) data = bld.pseudo(aco_opcode::p_create_vector, bld.def(RegType::vgpr, data.size() * 2), get_ssa_temp(ctx, instr->src[3].ssa), data); - Temp offset; - if (ctx->options->chip_class < GFX8) - offset = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa)); - else - offset = get_ssa_temp(ctx, instr->src[1].ssa); - + Temp offset = get_ssa_temp(ctx, instr->src[1].ssa); Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa)); rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));