From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 6 May 2019 04:12:09 +0000 (+0100)
Subject: LD/ST latches are async (clockless)
X-Git-Tag: ls180-24jan2020~1021
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=083b06406df21e502efc48d3885a1ca4552c8700;p=ieee754fpu.git

LD/ST latches are async (clockless)
---

diff --git a/src/scoreboard/ldst_dep_cell.py b/src/scoreboard/ldst_dep_cell.py
index ee998e91..f8d62308 100644
--- a/src/scoreboard/ldst_dep_cell.py
+++ b/src/scoreboard/ldst_dep_cell.py
@@ -35,8 +35,8 @@ class LDSTDepCell(Elaboratable):
 
     def elaborate(self, platform):
         m = Module()
-        m.submodules.war_l = war_l = SRLatch() # Write After Read Latch
-        m.submodules.raw_l = raw_l = SRLatch() # Read After Write Latch
+        m.submodules.war_l = war_l = SRLatch(sync=False) # WriteAfterRead Latch
+        m.submodules.raw_l = raw_l = SRLatch(sync=False) # ReadAfterWrite Latch
 
         # issue & store & load - used for both WAR and RAW Setting
         i_s_l = Signal(reset_less=True)