From: Sebastien Bourdeauducq Date: Thu, 30 May 2013 19:38:45 +0000 (+0200) Subject: dvisampler/clocking: remove DCM_CLKGEN X-Git-Tag: 24jan2021_ls180~2912 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=084aa64a2ae5fd01f310960b52604d5fc18138dc;p=litex.git dvisampler/clocking: remove DCM_CLKGEN --- diff --git a/milkymist/dvisampler/clocking.py b/milkymist/dvisampler/clocking.py index e718e4b1..07d4d490 100644 --- a/milkymist/dvisampler/clocking.py +++ b/milkymist/dvisampler/clocking.py @@ -16,19 +16,6 @@ class Clocking(Module, AutoCSR): ### - clk_dejitter = Signal() - dcm_locked = Signal() - self.specials += Instance("DCM_CLKGEN", - Instance.Parameter("CLKIN_PERIOD", 26.7), - Instance.Parameter("CLKFX_DIVIDE", 2), - Instance.Parameter("CLKFX_MULTIPLY", 2), - Instance.Parameter("CLKFX_MD_MAX", 1.0), - Instance.Input("CLKIN", pads.clk), - Instance.Input("RST", self._r_pll_reset.storage), - Instance.Output("CLKFX", clk_dejitter), - Instance.Output("LOCKED", dcm_locked) - ) - clkfbout = Signal() pll_locked = Signal() pll_clk0 = Signal() @@ -52,8 +39,8 @@ class Clocking(Module, AutoCSR): Instance.Output("CLKOUT3", pll_clk3), Instance.Output("LOCKED", pll_locked), Instance.Input("CLKFBIN", clkfbout), - Instance.Input("CLKIN", clk_dejitter), - Instance.Input("RST", ~dcm_locked) + Instance.Input("CLKIN", pads.clk), + Instance.Input("RST", self._r_pll_reset.storage) ) locked_async = Signal()