From: Dave Airlie <airlied@redhat.com>
Date: Fri, 1 Oct 2010 00:13:04 +0000 (+1000)
Subject: r600g: fix evergreen depth flushing.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=084c29baedf2702200b310d6e63a5d0f95aaac37;p=mesa.git

r600g: fix evergreen depth flushing.

although evergreen can apparantly sample direct from 24-bit,
just make it work with the current method for now.
---

diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 64fadb16e0b..5775b04cc7a 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -440,14 +440,11 @@ static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_conte
 	bo[1] = rbuffer->bo;
 	/* FIXME depth texture decompression */
 	if (tmp->depth) {
-#if 0
-		r = evergreen_texture_from_depth(ctx, tmp, view->first_level);
-		if (r) {
-			return;
-		}
-		bo[0] = radeon_ws_bo_incref(rscreen->rw, tmp->uncompressed);
-		bo[1] = radeon_ws_bo_incref(rscreen->rw, tmp->uncompressed);
-#endif
+		r600_texture_depth_flush(ctx, texture);
+		tmp = (struct r600_resource_texture*)texture;
+		rbuffer = &tmp->flushed_depth_texture->resource;
+		bo[0] = rbuffer->bo;
+		bo[1] = rbuffer->bo;
 	}
 	pitch = align(tmp->pitch[0] / tmp->bpt, 8);
 
@@ -852,6 +849,7 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
 	}
 	pipe_surface_reference(&rctx->framebuffer.zsbuf, state->zsbuf);
 	rctx->framebuffer = *state;
+	rctx->pframebuffer = &rctx->framebuffer;
 
 	/* build states */
 	for (int i = 0; i < state->nr_cbufs; i++) {
@@ -1645,3 +1643,41 @@ void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader
 			R_0288A4_SQ_PGM_START_FS,
 			0x00000000, 0xFFFFFFFF, shader->bo);
 }
+
+void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx)
+{
+	struct pipe_depth_stencil_alpha_state dsa;
+	struct r600_pipe_state *rstate;
+	boolean quirk = false;
+
+	if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
+		rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
+		quirk = true;
+
+	memset(&dsa, 0, sizeof(dsa));
+
+	if (quirk) {
+		dsa.depth.enabled = 1;
+		dsa.depth.func = PIPE_FUNC_LEQUAL;
+		dsa.stencil[0].enabled = 1;
+		dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
+		dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
+		dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
+		dsa.stencil[0].writemask = 0xff;
+	}
+
+	rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
+	r600_pipe_state_add_reg(rstate,
+				R_02880C_DB_SHADER_CONTROL,
+				0x0,
+				S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028000_DB_RENDER_CONTROL,
+				S_028000_DEPTH_COPY_ENABLE(1) |
+				S_028000_STENCIL_COPY_ENABLE(1) |
+				S_028000_COPY_CENTROID(1),
+				S_028000_DEPTH_COPY_ENABLE(1) |
+				S_028000_STENCIL_COPY_ENABLE(1) |
+				S_028000_COPY_CENTROID(1), NULL);
+	return rstate;
+}
diff --git a/src/gallium/drivers/r600/evergreend.h b/src/gallium/drivers/r600/evergreend.h
index 486cb29005d..54b26f6fb69 100644
--- a/src/gallium/drivers/r600/evergreend.h
+++ b/src/gallium/drivers/r600/evergreend.h
@@ -1424,8 +1424,16 @@
 #define R_008C0C_SQ_THREAD_RESOURCE_MGMT             0x00008C0C
 #define R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ        0x00008D8C
 #define R_028000_DB_RENDER_CONTROL                   0x00028000
+#define   S_028000_DEPTH_CLEAR_ENABLE(x)               (((x) & 0x1) << 0)
+#define   S_028000_STENCIL_CLEAR_ENABLE(x)             (((x) & 0x1) << 1)
+#define   S_028000_DEPTH_COPY_ENABLE(x)                (((x) & 0x1) << 2)
+#define   S_028000_STENCIL_COPY_ENABLE(x)              (((x) & 0x1) << 3)
+#define   S_028000_RESUMMARIZE_ENABLE(x)               (((x) & 0x1) << 4)
 #define   S_028000_STENCIL_COMPRESS_DISABLE(x)         (((x) & 0x1) << 5)
 #define   S_028000_DEPTH_COMPRESS_DISABLE(x)           (((x) & 0x1) << 6)
+#define   S_028000_COPY_CENTROID(x)                    (((x) & 0x1) << 7)
+#define   S_028000_COPY_SAMPLE(x)                      (((x) & 0x7) << 8)
+#define   S_028000_COLOR_DISABLE(x)                    (((x) & 0x1) << 12)
 #define R_028004_DB_COUNT_CONTROL                    0x00028004
 #define   S_028004_ZPASS_INCREMENT_DISABLE        (((x) & 0x1) << 0)
 #define   S_028004_PERFECT_ZPASS_COUNTS(x)        (((x) & 0x1) << 1)
diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c
index a25674b183c..1c23995123f 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -49,44 +49,6 @@
 /*
  * pipe_context
  */
-static void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx)
-{
-	struct pipe_depth_stencil_alpha_state dsa;
-	struct r600_pipe_state *rstate;
-	boolean quirk = false;
-
-	if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
-		rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
-		quirk = true;
-
-	memset(&dsa, 0, sizeof(dsa));
-
-	if (quirk) {
-		dsa.depth.enabled = 1;
-		dsa.depth.func = PIPE_FUNC_LEQUAL;
-		dsa.stencil[0].enabled = 1;
-		dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
-		dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
-		dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
-		dsa.stencil[0].writemask = 0xff;
-	}
-
-	rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
-	r600_pipe_state_add_reg(rstate,
-				R_02880C_DB_SHADER_CONTROL,
-				0x0,
-				S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
-	r600_pipe_state_add_reg(rstate,
-				R_028D0C_DB_RENDER_CONTROL,
-				S_028D0C_DEPTH_COPY_ENABLE(1) |
-				S_028D0C_STENCIL_COPY_ENABLE(1) |
-				S_028D0C_COPY_CENTROID(1),
-				S_028D0C_DEPTH_COPY_ENABLE(1) |
-				S_028D0C_STENCIL_COPY_ENABLE(1) |
-				S_028D0C_COPY_CENTROID(1), NULL);
-	return rstate;
-}
-
 static void r600_flush(struct pipe_context *ctx, unsigned flags,
 			struct pipe_fence_handle **fence)
 {
@@ -132,6 +94,7 @@ static struct pipe_context *r600_create_context(struct pipe_screen *screen, void
 {
 	struct r600_pipe_context *rctx = CALLOC_STRUCT(r600_pipe_context);
 	struct r600_screen* rscreen = (struct r600_screen *)screen;
+	enum chip_class class;
 
 	if (rctx == NULL)
 		return NULL;
@@ -210,7 +173,11 @@ static struct pipe_context *r600_create_context(struct pipe_screen *screen, void
 		return NULL;
 	}
 
-	rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
+	class = r600_get_family_class(rctx->radeon);
+	if (class == R600 || class == R700)
+		rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
+	else
+		rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
 
 	r600_blit_uncompress_depth_ptr = r600_blit_uncompress_depth;
 
diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h
index a3b8f66c092..18ebb0eb226 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -151,6 +151,7 @@ void evergreen_init_config(struct r600_pipe_context *rctx);
 void evergreen_draw(struct pipe_context *ctx, const struct pipe_draw_info *info);
 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
+void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx);
 
 /* r600_blit.c */
 void r600_init_blit_functions(struct r600_pipe_context *rctx);
@@ -190,7 +191,7 @@ void r600_translate_index_buffer(struct r600_pipe_context *r600,
 					struct pipe_resource **index_buffer,
 					unsigned *index_size,
 					unsigned *start, unsigned count);
-
+void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx);
 /* r600_helper.h */
 int r600_conv_pipe_prim(unsigned pprim, unsigned *prim);
 
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 23c2e5964a4..83eedd2040f 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -1524,3 +1524,41 @@ void r600_init_config(struct r600_pipe_context *rctx)
 	r600_pipe_state_add_reg(rstate, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0x00000000, 0xFFFFFFFF, NULL);
 	r600_context_pipe_state_set(&rctx->ctx, rstate);
 }
+
+void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx)
+{
+	struct pipe_depth_stencil_alpha_state dsa;
+	struct r600_pipe_state *rstate;
+	boolean quirk = false;
+
+	if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
+		rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
+		quirk = true;
+
+	memset(&dsa, 0, sizeof(dsa));
+
+	if (quirk) {
+		dsa.depth.enabled = 1;
+		dsa.depth.func = PIPE_FUNC_LEQUAL;
+		dsa.stencil[0].enabled = 1;
+		dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
+		dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
+		dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
+		dsa.stencil[0].writemask = 0xff;
+	}
+
+	rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
+	r600_pipe_state_add_reg(rstate,
+				R_02880C_DB_SHADER_CONTROL,
+				0x0,
+				S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028D0C_DB_RENDER_CONTROL,
+				S_028D0C_DEPTH_COPY_ENABLE(1) |
+				S_028D0C_STENCIL_COPY_ENABLE(1) |
+				S_028D0C_COPY_CENTROID(1),
+				S_028D0C_DEPTH_COPY_ENABLE(1) |
+				S_028D0C_STENCIL_COPY_ENABLE(1) |
+				S_028D0C_COPY_CENTROID(1), NULL);
+	return rstate;
+}