From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 4 Oct 2020 13:08:43 +0000 (+0000)
Subject: update experiment4 to use pads.useCoreSize
X-Git-Tag: partial-core-ls180-gdsii~45
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0867eeb028bfe13e5c023407f5bc793a00ea37ab;p=soclayout.git

update experiment4 to use pads.useCoreSize
---

diff --git a/experiments4/coriolis2/ioring.py b/experiments4/coriolis2/ioring.py
index b362811..5b43d14 100644
--- a/experiments4/coriolis2/ioring.py
+++ b/experiments4/coriolis2/ioring.py
@@ -31,8 +31,9 @@ chip = { 'pads.ioPadGauge' : 'pxlib',
             [ 'p_b1', 'p_vddeck_0', 'p_b0'        , 'p_vsseck_0', 'rst' ],
        'pads.west'       :
             [ 'p_f3', 'p_f2'       , 'p_clk_0', 'p_f1'       , 'p_f0' ],
-       'core.size'       : ( l( 800), l( 800) ),
-       'chip.size'       : ( l(2000), l(2000) ),
+       'core.size'       : ( l( 1200), l( 1200) ),
+       'chip.size'       : ( l(3200), l(3200) ),
+       'pads.useCoreSize'  : True,
        'chip.clockTree'  : True,
        }