From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Thu, 4 Jul 2013 17:25:29 +0000 (+0200)
Subject: Do not specify period constraints twice
X-Git-Tag: 24jan2021_ls180~2099^2~443^2~18
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0883e99de3aad61fa98a73a5e61d9785ee5668e2;p=litex.git

Do not specify period constraints twice
---

diff --git a/mibuild/platforms/m1.py b/mibuild/platforms/m1.py
index 80d61a14..a096a38a 100644
--- a/mibuild/platforms/m1.py
+++ b/mibuild/platforms/m1.py
@@ -119,7 +119,7 @@ _io = [
 class Platform(XilinxISEPlatform):
 	def __init__(self):
 		XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-2", _io,
-			lambda p: CRG_SE(p, "clk50", "user_btn", 20.0))
+			lambda p: CRG_SE(p, "clk50", "user_btn"))
 
 	def do_finalize(self, fragment):
 		try:
diff --git a/mibuild/platforms/mixxeo.py b/mibuild/platforms/mixxeo.py
index ebf87c3c..4ea76460 100644
--- a/mibuild/platforms/mixxeo.py
+++ b/mibuild/platforms/mixxeo.py
@@ -143,7 +143,7 @@ _io = [
 class Platform(XilinxISEPlatform):
 	def __init__(self):
 		XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-3", _io,
-			lambda p: CRG_SE(p, "clk50", None, 20.0))
+			lambda p: CRG_SE(p, "clk50", None))
 		self.add_platform_command("CONFIG VCCAUX=\"3.3\";\n")
 
 	def do_finalize(self, fragment):
diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py
index 2bc8c107..2ff3abec 100644
--- a/mibuild/xilinx_ise.py
+++ b/mibuild/xilinx_ise.py
@@ -10,16 +10,17 @@ from mibuild.crg import SimpleCRG
 from mibuild import tools
 
 def _add_period_constraint(platform, clk, period):
-	platform.add_platform_command("""NET "{clk}" TNM_NET = "GRPclk";
+	if period is not None:
+		platform.add_platform_command("""NET "{clk}" TNM_NET = "GRPclk";
 TIMESPEC "TSclk" = PERIOD "GRPclk" """+str(period)+""" ns HIGH 50%;""", clk=clk)
 
 class CRG_SE(SimpleCRG):
-	def __init__(self, platform, clk_name, rst_name, period, rst_invert=False):
+	def __init__(self, platform, clk_name, rst_name, period=None, rst_invert=False):
 		SimpleCRG.__init__(self, platform, clk_name, rst_name, rst_invert)
 		_add_period_constraint(platform, self._clk, period)
 
 class CRG_DS(Module):
-	def __init__(self, platform, clk_name, rst_name, period, rst_invert=False):
+	def __init__(self, platform, clk_name, rst_name, period=None, rst_invert=False):
 		reset_less = rst_name is None
 		self.clock_domains.cd_sys = ClockDomain(reset_less=reset_less)
 		self._clk = platform.request(clk_name)