From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 18 Sep 2022 13:29:50 +0000 (+0100)
Subject: remove subvector mode from sv/trans/svp64.py
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=088d065def6f84f3457b83059c5b19585c15c527;p=openpower-isa.git

remove subvector mode from sv/trans/svp64.py
---

diff --git a/src/openpower/consts.py b/src/openpower/consts.py
index 3a5e2c8e..86c4bdb7 100644
--- a/src/openpower/consts.py
+++ b/src/openpower/consts.py
@@ -242,13 +242,10 @@ class SVP64MODEb(_Const):
     MOD2_MSB = 0
     MOD2_LSB = 1
     MOD3 = 3
-    # pack detection (TODO, CR-ops needs one of these too)
-    LDST_PACK = 2 # set =1 for LD/ST-immediate Pack mode
-    ARITH_PACK = 4 # set =1 for Arithmetic Pack mode
     # when predicate not set: 0=ignore/skip 1=zero
     DZ = 3  # for destination
     SZ = 4  # for source
-    ZZ = 3  # for both sz/dz, on all but CR-ops
+    ZZ = 3  # for both sz/dz, on all but CR-ops, which, whoops, is RM bit 6.
     # for branch-conditional
     BC_SNZ = 3  # for branch-conditional mode
     BC_VLI = 2  # for VL include/exclude on VLSET mode
@@ -256,7 +253,6 @@ class SVP64MODEb(_Const):
     BC_CTRTEST = 0 # CTR-test mode
     # reduce mode
     REDUCE = 2  # 0=normal predication 1=reduce mode
-    SVM = 3  # subvector reduce mode 0=independent 1=horizontal
     CRM = 4  # CR mode on reduce (Rc=1) 0=some 1=all
     RG = 4   # Reverse-gear on reduce
     # saturation mode
diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index 8ec257b9..dda0576c 100644
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -1049,7 +1049,6 @@ class SVP64Asm:
         mapreduce = False
         reverse_gear = False
         mapreduce_crm = False
-        mapreduce_svm = False
 
         predresult = False
         failfirst = False
@@ -1143,8 +1142,6 @@ class SVP64Asm:
                 assert sv_mode is None
                 sv_mode = 0b00
                 mapreduce_crm = True
-            elif encmode == 'svm':  # sub-vector mode
-                mapreduce_svm = True
             elif is_bc:
                 if encmode == 'all':
                     bc_all = 1
@@ -1206,9 +1203,6 @@ class SVP64Asm:
                 "dest-mask can only be specified on Twin-predicate ops"
 
         # construct the mode field, doing sanity-checking along the way
-        if mapreduce_svm:
-            assert sv_mode == 0b00, "sub-vector mode in mapreduce only"
-            assert subvl != 0, "sub-vector mode not possible on SUBVL=1"
 
         if src_zero:
             assert has_smask or mask_m_specified, \
@@ -1227,9 +1221,7 @@ class SVP64Asm:
             | 0-1 |  2  |  3   4  |  description              |
             | --- | --- |---------|-------------------------- |
             | 00  |   0 |  dz  sz | simple mode                      |
-            | 00  |   1 | 0  RG   | scalar reduce mode (mapreduce), SUBVL=1 |
-            | 00  |   1 | SVM 0   | subvector reduce mode, SUBVL>1   |
-            | 00  |   1 | /   1   | reserved |
+            | 00  |   1 | 0  RG   | scalar reduce mode (mapreduce) |
             | 01  | inv | CR-bit  | Rc=1: ffirst CR sel              |
             | 01  | inv | VLi RC1 |  Rc=0: ffirst z/nonz |
             | 10  |   N | dz   sz |  sat mode: N=0/1 u/s |
@@ -1307,8 +1299,6 @@ class SVP64Asm:
                 # SVM mode can be enabled only when SUBVL=2/3/4 (vec2/3/4)
                 if subvl == 0:
                     mode |= dst_zero << SVP64MODE.DZ  # predicate zeroing
-                elif mapreduce_svm:
-                    mode |= (0b1 << SVP64MODE.SVM)  # sets SVM mode
 
             ######################################
             # "failfirst" modes