From: Cesar Strauss <cestrauss@gmail.com>
Date: Sat, 4 Jul 2020 14:45:36 +0000 (-0300)
Subject: Begin a new parallel test
X-Git-Tag: div_pipeline~162^2~48
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=08964401e2bb5c15debf6b8d4021bbe23b44a40c;p=soc.git

Begin a new parallel test

The purpose of this test is really to better develop a
parallel test concept, by testing against a simple
target.
---

diff --git a/src/soc/experiment/alu_hier.py b/src/soc/experiment/alu_hier.py
index 5dcf958c..b98a39fb 100644
--- a/src/soc/experiment/alu_hier.py
+++ b/src/soc/experiment/alu_hier.py
@@ -14,6 +14,7 @@ from nmigen.hdl.rec import Record, Layout
 from nmigen.cli import main
 from nmigen.cli import verilog, rtlil
 from nmigen.compat.sim import run_simulation
+from nmigen.back.pysim import Simulator
 
 from soc.decoder.power_enums import InternalOp, Function, CryIn
 
@@ -472,8 +473,28 @@ def test_alu():
         f.write(vl)
 
 
+def test_alu_parallel():
+    m = Module()
+    m.submodules.alu = alu = ALU(width=16)
+    sim = Simulator(m)
+    sim.add_clock(1e-6)
+
+    def process():
+        yield
+
+    sim.add_sync_process(process)
+    sim_writer = sim.write_vcd(
+        "test_alu_parallel.vcd",
+        "test_alu_parallel.gtkw",
+        traces=alu.ports()
+    )
+    with sim_writer:
+        sim.run()
+
+
 if __name__ == "__main__":
     test_alu()
+    test_alu_parallel()
 
     # alu = BranchALU(width=16)
     # vl = rtlil.convert(alu, ports=alu.ports())