From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 28 Feb 2021 16:21:42 +0000 (+0000)
Subject: add SVP64 RM sub-field enums
X-Git-Tag: convert-csv-opcode-to-binary~140
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=089d2d7919f3a9667a0e1fc72454c47f22a1bb6f;p=soc.git

add SVP64 RM sub-field enums
---

diff --git a/src/soc/decoder/power_enums.py b/src/soc/decoder/power_enums.py
index 32bd638e..0cee6124 100644
--- a/src/soc/decoder/power_enums.py
+++ b/src/soc/decoder/power_enums.py
@@ -135,6 +135,37 @@ class SVEXTRA(Enum):
     Idx3 = 4
     Idx_1_2 = 5 # due to weird BA/BB for crops
 
+@unique
+class SVP64PredInt(Enum):
+    ALWAYS = 0
+    R3_UNARY = 1
+    R3 = 2
+    R3_N = 3
+    R10 = 4
+    R10_N = 5
+    R30 = 6
+    R30_N = 7
+
+@unique
+class SVP64PredCR(Enum):
+    LT = 0
+    GE = 1
+    GT = 2
+    LE = 3
+    EQ = 4
+    NE = 5
+    SO = 6
+    NS = 7
+
+@unique
+class SVP64RMMode(Enum):
+    NORMAL = 0
+    MAPREDUCE = 1
+    FFIRST = 2
+    SATURATE = 3
+    PREDRES = 4
+
+
 # supported instructions: make sure to keep up-to-date with CSV files
 # just like everything else
 _insns = [
diff --git a/src/soc/sv/svp64.py b/src/soc/sv/svp64.py
index 3911fb4c..d9933215 100644
--- a/src/soc/sv/svp64.py
+++ b/src/soc/sv/svp64.py
@@ -1,19 +1,19 @@
 # SPDX-License-Identifier: LGPLv3+
 # Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 # Funded by NLnet http://nlnet.nl
-"""SVP64 RM (Remap) Record.  
+"""SVP64 RM (Remap) Record.
 
 https://libre-soc.org/openpower/sv/svp64/
 
-| Field Name | Field bits | Description                            |
-|------------|------------|----------------------------------------|
-| MASKMODE   | `0`        | Execution (predication) Mask Kind      |
-| MASK          | `1:3`      | Execution Mask                      |
-| ELWIDTH       | `4:5`      | Element Width                       |
-| ELWIDTH_SRC   | `6:7`      | Element Width for Source            |
-| SUBVL         | `8:9`      | Sub-vector length                   |  
-| EXTRA         | `10:18`    | context-dependent extra             |
-| MODE          | `19:23`    | changes Vector behaviour            |
+| Field Name  | Field bits | Description                            |
+|-------------|------------|----------------------------------------|
+| MASKMODE    | `0`        | Execution (predication) Mask Kind      |
+| MASK        | `1:3`      | Execution Mask                         |
+| ELWIDTH     | `4:5`      | Element Width                          |
+| ELWIDTH_SRC | `6:7`      | Element Width for Source               |
+| SUBVL       | `8:9`      | Sub-vector length                      |
+| EXTRA       | `10:18`    | context-dependent extra                |
+| MODE        | `19:23`    | changes Vector behaviour               |
 """
 
 from nmigen import Record
@@ -34,3 +34,23 @@ class SVP64Rec(Record):
         return [self.mmode, self.mask, self.elwidth, self.ewsrc,
                 self.extra, self.mode]
 
+"""RM Mode
+
+LD/ST:
+00	str	sz dz	normal mode
+01	inv	CR-bit	Rc=1: ffirst CR sel
+01	inv	els RC1	Rc=0: ffirst z/nonz
+10	N	sz els	sat mode: N=0/1 u/s
+11	inv	CR-bit	Rc=1: pred-result CR sel
+11	inv	els RC1	Rc=0: pred-result z/nonz
+
+Arithmetic:
+00	0	sz dz	normal mode
+00	1	sz CRM	reduce mode (mapreduce), SUBVL=1
+00	1	SVM CRM	subvector reduce mode, SUBVL>1
+01	inv	CR-bit	Rc=1: ffirst CR sel
+01	inv	sz RC1	Rc=0: ffirst z/nonz
+10	N	sz dz	sat mode: N=0/1 u/s
+11	inv	CR-bit	Rc=1: pred-result CR sel
+11	inv	sz RC1	Rc=0: pred-result z/nonz
+"""