From: Andrew Waterman Date: Tue, 12 Jul 2016 00:45:16 +0000 (-0700) Subject: Remove instruction width assumptions to support RVC X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=089f4aae4836af1f3f530fbedc3a43a685eae0d1;p=riscv-tests.git Remove instruction width assumptions to support RVC --- diff --git a/env b/env index 92fb0bd..ae484b6 160000 --- a/env +++ b/env @@ -1 +1 @@ -Subproject commit 92fb0bd7d7d2723f90896bb351f5cdb0eb36b73b +Subproject commit ae484b6ab8aec310ecb0ca9a46704a709d0ef99d diff --git a/isa/rv32ui/fence_i.S b/isa/rv32ui/fence_i.S index 8785c1e..cd1dbc3 100644 --- a/isa/rv32ui/fence_i.S +++ b/isa/rv32ui/fence_i.S @@ -1,53 +1,7 @@ # See LICENSE for license details. -#***************************************************************************** -# fence_i.S -#----------------------------------------------------------------------------- -# -# Test self-modifying code and the fence.i instruction. -# - #include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - -li a3, 111 -la a0, 3f -la a1, 1f -la a2, 2f -lw a0, 0(a0) - -# test I$ hit -.align 6 -sw a0, 0(a1) -fence.i - -1: addi a3, a3, 222 -TEST_CASE( 2, a3, 444, nop ) - -# test prefetcher hit -li a4, 100 -1: addi a4, a4, -1 -bnez a4, 1b - -sw a0, 0(a2) -fence.i - -.align 6 -2: addi a3, a3, 555 -TEST_CASE( 3, a3, 777, nop ) - -3: addi a3, a3, 333 - -TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U -RVTEST_DATA_END +#include "../rv64ui/fence_i.S" diff --git a/isa/rv64mi/dirty.S b/isa/rv64mi/dirty.S index 66ed5a0..0314cf5 100644 --- a/isa/rv64mi/dirty.S +++ b/isa/rv64mi/dirty.S @@ -52,6 +52,7 @@ RVTEST_CODE_BEGIN TEST_PASSFAIL + .align 2 stvec_handler: csrr t0, scause li t1, 2 diff --git a/isa/rv64mi/ma_addr.S b/isa/rv64mi/ma_addr.S index ed177f5..c84242a 100644 --- a/isa/rv64mi/ma_addr.S +++ b/isa/rv64mi/ma_addr.S @@ -14,6 +14,7 @@ RVTEST_RV64M RVTEST_CODE_BEGIN .align 3 + .option norvc auipc s0, 0 # indicate it's a load test diff --git a/isa/rv64si/csr.S b/isa/rv64si/csr.S index 35fc99a..3858daa 100644 --- a/isa/rv64si/csr.S +++ b/isa/rv64si/csr.S @@ -61,6 +61,7 @@ RVTEST_CODE_BEGIN # We should only fall through to this if scall failed. TEST_PASSFAIL + .align 2 stvec_handler: # Trapping on tests 10 and 11 is good news. # Note that since the test didn't complete, TESTNUM is smaller by 1. diff --git a/isa/rv64si/ma_fetch.S b/isa/rv64si/ma_fetch.S index a97eecb..544daa0 100644 --- a/isa/rv64si/ma_fetch.S +++ b/isa/rv64si/ma_fetch.S @@ -63,6 +63,7 @@ RVTEST_CODE_BEGIN TEST_PASSFAIL + .align 2 stvec_handler: # tests 2 and 4 should trap li a0, 2 diff --git a/isa/rv64si/sbreak.S b/isa/rv64si/sbreak.S index 99240be..c2a6e49 100644 --- a/isa/rv64si/sbreak.S +++ b/isa/rv64si/sbreak.S @@ -23,21 +23,18 @@ RVTEST_CODE_BEGIN #endif li TESTNUM, 2 + sbreak j fail - j pass - TEST_PASSFAIL + .align 2 stvec_handler: li t1, CAUSE_BREAKPOINT csrr t0, scause bne t0, t1, fail - csrr t0, sepc - addi t0, t0, 8 - csrw sepc, t0 - sret + j pass RVTEST_CODE_END diff --git a/isa/rv64si/scall.S b/isa/rv64si/scall.S index f4752d1..82ba7c0 100644 --- a/isa/rv64si/scall.S +++ b/isa/rv64si/scall.S @@ -39,6 +39,7 @@ RVTEST_CODE_BEGIN TEST_PASSFAIL + .align 2 stvec_handler: li t1, CAUSE_USER_ECALL csrr t0, scause diff --git a/isa/rv64ui/fence_i.S b/isa/rv64ui/fence_i.S index 2c51c9c..f2076c8 100644 --- a/isa/rv64ui/fence_i.S +++ b/isa/rv64ui/fence_i.S @@ -22,6 +22,7 @@ lw a0, 0(a0) # test I$ hit .align 6 sw a0, 0(a1) +.align 2 fence.i 1: addi a3, a3, 222 diff --git a/isa/rv64ui/jalr.S b/isa/rv64ui/jalr.S index 210973e..d63bbe2 100644 --- a/isa/rv64ui/jalr.S +++ b/isa/rv64ui/jalr.S @@ -42,6 +42,8 @@ target_2: # Test delay slot instructions not executed nor bypassed #------------------------------------------------------------- + .option push + .option norvc TEST_CASE( 7, t0, 4, \ li t0, 1; \ la t1, 1f; \ @@ -53,6 +55,7 @@ target_2: 1: addi t0, t0, 1; \ addi t0, t0, 1; \ ) + .option pop TEST_PASSFAIL