From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 1 Sep 2022 16:16:20 +0000 (+0100)
Subject: update CSV files marking those instructions that are RC-only as such
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=08af7c3b712bf64341b5908b230d7c588d8114d1;p=openpower-isa.git

update CSV files marking those instructions that are RC-only as such
there were actually some bugs here, entries that had not been added to
DecodeOE such as (all!) fp operations (which have no OE=1 variant)
and the new AV abs/min/max instructions
---

diff --git a/openpower/isatables/minor_22.csv b/openpower/isatables/minor_22.csv
index a0207c06..951ef6f9 100644
--- a/openpower/isatables/minor_22.csv
+++ b/openpower/isatables/minor_22.csv
@@ -1,23 +1,23 @@
 # all of these are DRAFT instructions, not yet submitted to the OPF ISA WG
 opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form,CONDITIONS,unofficial,comment2
 # Simple-V Scalable Vector
------11011-,VL,OP_SETVL,RA_OR_ZERO,NONE,NONE,RT_OR_ZERO,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,setvl,SVL,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+-----11011-,VL,OP_SETVL,RA_OR_ZERO,NONE,NONE,RT_OR_ZERO,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,setvl,SVL,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 -----011001,VL,OP_SVSHAPE,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,svshape,SVM,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 -----101001,VL,OP_SVINDEX,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,svindex,SVI,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 -----111001,VL,OP_SVREMAP,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,svremap,SVRM,,1,unofficial until submitted and approved/renumbered by the opf isa wg
------10011-,VL,OP_SVSTEP,NONE,NONE,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,svstep,SVL,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+-----10011-,VL,OP_SVSTEP,NONE,NONE,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,svstep,SVL,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 # A/V bitmanip
-0111001110-,ALU,OP_MINMAX,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,maxs,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-0011001110-,ALU,OP_MINMAX,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,maxu,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-0101001110-,ALU,OP_MINMAX,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,mins,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-0001001110-,ALU,OP_MINMAX,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,minu,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-1101001110-,ALU,OP_AVGADD,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,avgadd,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-1011110110-,ALU,OP_ABSDIFF,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,absdu,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-1001110110-,ALU,OP_ABSDIFF,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,absds,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-1111110110-,ALU,OP_ABSADD,RA,RB,RT,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,absdacu,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-0111110110-,ALU,OP_ABSADD,RA,RB,RT,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,absdacs,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+0111001110-,ALU,OP_MINMAX,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,maxs,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+0011001110-,ALU,OP_MINMAX,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,maxu,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+0101001110-,ALU,OP_MINMAX,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,mins,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+0001001110-,ALU,OP_MINMAX,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,minu,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+1101001110-,ALU,OP_AVGADD,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,avgadd,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+1011110110-,ALU,OP_ABSDIFF,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,absdu,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+1001110110-,ALU,OP_ABSDIFF,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,absds,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+1111110110-,ALU,OP_ABSADD,RA,RB,RT,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,absdacu,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+0111110110-,ALU,OP_ABSADD,RA,RB,RT,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,absdacs,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 # Vector bitmanip
-0110001110-,ALU,OP_CPROP,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,cprop,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+0110001110-,ALU,OP_CPROP,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,cprop,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 ------10001,ALU,OP_BMASK,RA,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,bmask,BM2,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 -----00011-,ALU,OP_FMVIS,NONE,CONST_UI,NONE,FRS,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,fmvis,DX,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 -----01011-,ALU,OP_FISHMV,FRS,CONST_UI,NONE,FRS,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,fishmv,DX,,1,unofficial until submitted and approved/renumbered by the opf isa wg
diff --git a/openpower/isatables/minor_30.csv b/openpower/isatables/minor_30.csv
index cb68d552..9af910d2 100644
--- a/openpower/isatables/minor_30.csv
+++ b/openpower/isatables/minor_30.csv
@@ -1,9 +1,9 @@
 # SPDX-License-Header: CC-BY-4
 # derived from microwatt decode1.vhdl, with thanks and gratitude (IBM, OPF)
 opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form,CONDITIONS
-010-,SHIFT_ROT,OP_RLC,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldic,MD,
-000-,SHIFT_ROT,OP_RLCL,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldicl,MDS,
-001-,SHIFT_ROT,OP_RLCR,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldicr,MD,
-011-,SHIFT_ROT,OP_RLC,RA,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldimi,MD,
-1000,SHIFT_ROT,OP_RLCL,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldcl,MD,
-1001,SHIFT_ROT,OP_RLCR,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldcr,MD,
+010-,SHIFT_ROT,OP_RLC,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,rldic,MD,
+000-,SHIFT_ROT,OP_RLCL,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,rldicl,MDS,
+001-,SHIFT_ROT,OP_RLCR,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,rldicr,MD,
+011-,SHIFT_ROT,OP_RLC,RA,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,rldimi,MD,
+1000,SHIFT_ROT,OP_RLCL,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,rldcl,MD,
+1001,SHIFT_ROT,OP_RLCR,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,rldcr,MD,
diff --git a/openpower/isatables/minor_31.csv b/openpower/isatables/minor_31.csv
index 5cd8494d..b1d45b1e 100644
--- a/openpower/isatables/minor_31.csv
+++ b/openpower/isatables/minor_31.csv
@@ -50,11 +50,11 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 0b1111101011,DIV,OP_DIV,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,1,RC,0,0,divwo,XO,
 0b1101010110,ALU,OP_NOP,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,eieio,X,
 0b0100011100,LOGICAL,OP_XOR,RS,RB,NONE,RA,NONE,CR0,0,1,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,eqv,X,
-0b1110111010,ALU,OP_EXTS,RS,NONE,NONE,RA,NONE,CR0,0,0,ZERO,0,is1B,0,0,0,0,0,0,RC,0,0,extsb,X,
-0b1110011010,ALU,OP_EXTS,RS,NONE,NONE,RA,NONE,CR0,0,0,ZERO,0,is2B,0,0,0,0,0,0,RC,0,0,extsh,X,
-0b1111011010,ALU,OP_EXTS,RS,NONE,NONE,RA,NONE,CR0,0,0,ZERO,0,is4B,0,0,0,0,0,0,RC,0,0,extsw,X,
-0b1101111010,SHIFT_ROT,OP_EXTSWSLI,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,extswsli,XS,
-0b1101111011,SHIFT_ROT,OP_EXTSWSLI,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,extswsli,XS,
+0b1110111010,ALU,OP_EXTS,RS,NONE,NONE,RA,NONE,CR0,0,0,ZERO,0,is1B,0,0,0,0,0,0,RC_ONLY,0,0,extsb,X,
+0b1110011010,ALU,OP_EXTS,RS,NONE,NONE,RA,NONE,CR0,0,0,ZERO,0,is2B,0,0,0,0,0,0,RC_ONLY,0,0,extsh,X,
+0b1111011010,ALU,OP_EXTS,RS,NONE,NONE,RA,NONE,CR0,0,0,ZERO,0,is4B,0,0,0,0,0,0,RC_ONLY,0,0,extsw,X,
+0b1101111010,SHIFT_ROT,OP_EXTSWSLI,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,extswsli,XS,
+0b1101111011,SHIFT_ROT,OP_EXTSWSLI,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,extswsli,XS,
 0b1111010110,ALU,OP_ICBI,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,icbi,X,
 0b0000010110,ALU,OP_NOP,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,icbt,X,
 0b0000001111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A,
@@ -131,14 +131,14 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 0b0010110010,TRAP,OP_MTMSRD,RS,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,mtmsrd,X,
 0b0010010010,TRAP,OP_MTMSR,RS,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,mtmsr,X,
 0b0111010011,SPR,OP_MTSPR,RS,NONE,NONE,SPR,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,mtspr,XFX,
-0b0001001001,MUL,OP_MUL_H64,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,1,RC,0,0,mulhd,XO,
-0b0000001001,MUL,OP_MUL_H64,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,mulhdu,XO,
-0b0001001011,MUL,OP_MUL_H32,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,1,RC,0,0,mulhw,XO,
-0b0000001011,MUL,OP_MUL_H32,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,mulhwu,XO,
-0b1001001001,MUL,OP_MUL_H64,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,1,RC,0,0,mulhd,XO,
-0b1000001001,MUL,OP_MUL_H64,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,mulhdu,XO,
-0b1001001011,MUL,OP_MUL_H32,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,1,RC,0,0,mulhw,XO,
-0b1000001011,MUL,OP_MUL_H32,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,mulhwu,XO,
+0b0001001001,MUL,OP_MUL_H64,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,1,RC_ONLY,0,0,mulhd,XO,
+0b0000001001,MUL,OP_MUL_H64,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,mulhdu,XO,
+0b0001001011,MUL,OP_MUL_H32,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,1,RC_ONLY,0,0,mulhw,XO,
+0b0000001011,MUL,OP_MUL_H32,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,mulhwu,XO,
+0b1001001001,MUL,OP_MUL_H64,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,1,RC_ONLY,0,0,mulhd,XO,
+0b1000001001,MUL,OP_MUL_H64,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,mulhdu,XO,
+0b1001001011,MUL,OP_MUL_H32,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,1,RC_ONLY,0,0,mulhw,XO,
+0b1000001011,MUL,OP_MUL_H32,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,mulhwu,XO,
 0b0011101001,MUL,OP_MUL_L64,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,1,RC,0,0,mulld,XO,
 0b1011101001,MUL,OP_MUL_L64,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,1,RC,0,0,mulldo,XO,
 0b0011101011,MUL,OP_MUL_L64,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,1,RC,0,0,mullw,XO,
@@ -156,18 +156,18 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 0b0010011010,LOGICAL,OP_PRTY,RS,NONE,NONE,RA,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,0,prtyw,X,
 0b0010000000,CR,OP_SETB,NONE,NONE,NONE,RT,BFA,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,setb,VX,
 0b0111110010,MMU,OP_TLBIE,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,slbia,X,
-0b0000011011,SHIFT_ROT,OP_SHL,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,sld,X,
-0b0000011000,SHIFT_ROT,OP_SHL,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,slw,X,
-0b1100011010,SHIFT_ROT,OP_SHR,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,1,NONE,0,0,0,0,0,1,RC,0,0,srad,X,
-0b1100111010,SHIFT_ROT,OP_SHR,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,1,NONE,0,0,0,0,0,1,RC,0,0,sradi,XS,
-0b1100111011,SHIFT_ROT,OP_SHR,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,1,NONE,0,0,0,0,0,1,RC,0,0,sradi,XS,
-0b1100011000,SHIFT_ROT,OP_SHR,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,1,NONE,0,0,0,0,1,1,RC,0,0,sraw,X,
-0b1100111000,SHIFT_ROT,OP_SHR,NONE,CONST_SH32,RS,RA,NONE,CR0,0,0,ZERO,1,NONE,0,0,0,0,1,1,RC,0,0,srawi,X,
-0b1000011011,SHIFT_ROT,OP_SHR,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,srd,X,
-0b1000011000,SHIFT_ROT,OP_SHR,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,srw,X,
+0b0000011011,SHIFT_ROT,OP_SHL,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,sld,X,
+0b0000011000,SHIFT_ROT,OP_SHL,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,slw,X,
+0b1100011010,SHIFT_ROT,OP_SHR,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,1,NONE,0,0,0,0,0,1,RC_ONLY,0,0,srad,X,
+0b1100111010,SHIFT_ROT,OP_SHR,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,1,NONE,0,0,0,0,0,1,RC_ONLY,0,0,sradi,XS,
+0b1100111011,SHIFT_ROT,OP_SHR,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,1,NONE,0,0,0,0,0,1,RC_ONLY,0,0,sradi,XS,
+0b1100011000,SHIFT_ROT,OP_SHR,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,1,NONE,0,0,0,0,1,1,RC_ONLY,0,0,sraw,X,
+0b1100111000,SHIFT_ROT,OP_SHR,NONE,CONST_SH32,RS,RA,NONE,CR0,0,0,ZERO,1,NONE,0,0,0,0,1,1,RC_ONLY,0,0,srawi,X,
+0b1000011011,SHIFT_ROT,OP_SHR,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,srd,X,
+0b1000011000,SHIFT_ROT,OP_SHR,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,srw,X,
 0b1111010101,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is1B,0,0,cix,0,0,0,NONE,0,1,stbcix,X,
 0b1010110110,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,CR0,0,0,ZERO,0,is1B,0,0,0,1,0,0,ONE,0,1,stbcx,X,
-0b0011110111,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is1B,0,0,1,0,0,0,RC,0,1,stbux,X,
+0b0011110111,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is1B,0,0,1,0,0,0,NONE,0,1,stbux,X,
 0b0011010111,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is1B,0,0,0,0,0,0,NONE,0,1,stbx,X,
 0b1010010100,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is8B,1,0,0,0,0,0,NONE,0,1,stdbrx,X,
 0b1111110101,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is8B,0,0,cix,0,0,0,NONE,0,1,stdcix,X,
diff --git a/openpower/isatables/minor_5.csv b/openpower/isatables/minor_5.csv
index 071cc999..87baf549 100644
--- a/openpower/isatables/minor_5.csv
+++ b/openpower/isatables/minor_5.csv
@@ -1,6 +1,6 @@
 opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form,CONDITIONS,unofficial,comment2
---------00-,SHIFT_ROT,OP_TERNLOG,RA,RB,RT,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,ternlogi,TLI,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-0010010110-,SHIFT_ROT,OP_GREV,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,grev,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
--011010110-,SHIFT_ROT,OP_GREV,RA,CONST_XBI,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,grevi,XB,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-0010110110-,SHIFT_ROT,OP_GREV,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,grevw,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-0011110110-,SHIFT_ROT,OP_GREV,RA,CONST_SH32,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,grevwi,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+--------00-,SHIFT_ROT,OP_TERNLOG,RA,RB,RT,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,ternlogi,TLI,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+0010010110-,SHIFT_ROT,OP_GREV,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,grev,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+-011010110-,SHIFT_ROT,OP_GREV,RA,CONST_XBI,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,grevi,XB,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+0010110110-,SHIFT_ROT,OP_GREV,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,grevw,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+0011110110-,SHIFT_ROT,OP_GREV,RA,CONST_SH32,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,grevwi,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
diff --git a/openpower/isatables/minor_59.csv b/openpower/isatables/minor_59.csv
index b142c037..0f0cb8d6 100644
--- a/openpower/isatables/minor_59.csv
+++ b/openpower/isatables/minor_59.csv
@@ -1,24 +1,24 @@
 # SPDX-License-Header: CC-BY-4
 # derived from microwatt decode1.vhdl, with thanks and gratitude (IBM, OPF)
 opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form,CONDITIONS,unofficial,comment2
-1101001110,FPU,OP_FPOP_I,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fcfids,X,,,
-1111001110,FPU,OP_FPOP_I,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fcfidus,X,,,
------10010,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fdivs,A,,,
------10100,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fsubs,A,,,
------10101,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fadds,A,,,
------10110,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fsqrts,A,,,
------11000,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fres,A,,,
------11001,FPU,OP_FPOP,FRA,NONE,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fmuls,A,,,
------11010,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,frsqrtes,A,,,
------11100,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fmsubs,A,,,
------11101,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fmadds,A,,,
------11110,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fnmsubs,A,,,
------11111,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fnmadds,A,,,
------00100,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,ffmsubs,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg
------00101,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,ffmadds,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg
------00110,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,ffnmsubs,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg
------00111,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,ffnmadds,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg
------01101,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,ffadds,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg
------01111,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fdmadds,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-1000001110,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fsins,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-1000101110,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fcoss,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+1101001110,FPU,OP_FPOP_I,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fcfids,X,,,
+1111001110,FPU,OP_FPOP_I,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fcfidus,X,,,
+-----10010,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fdivs,A,,,
+-----10100,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fsubs,A,,,
+-----10101,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fadds,A,,,
+-----10110,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fsqrts,A,,,
+-----11000,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fres,A,,,
+-----11001,FPU,OP_FPOP,FRA,NONE,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmuls,A,,,
+-----11010,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,frsqrtes,A,,,
+-----11100,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmsubs,A,,,
+-----11101,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmadds,A,,,
+-----11110,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fnmsubs,A,,,
+-----11111,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fnmadds,A,,,
+-----00100,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,ffmsubs,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+-----00101,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,ffmadds,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+-----00110,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,ffnmsubs,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+-----00111,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,ffnmadds,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+-----01101,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,ffadds,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+-----01111,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fdmadds,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+1000001110,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fsins,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+1000101110,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fcoss,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
diff --git a/openpower/isatables/minor_63.csv b/openpower/isatables/minor_63.csv
index 4b26ce2b..04ffb124 100644
--- a/openpower/isatables/minor_63.csv
+++ b/openpower/isatables/minor_63.csv
@@ -6,42 +6,42 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 0001000000,FPU,OP_FPOP,NONE,NONE,NONE,NONE,NONE,BF,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,2/0=mcrfs,X,
 0010000000,FPU,OP_FPOP,FRA,FRB,NONE,NONE,NONE,BF,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,4/0=ftdiv,X,
 0010100000,FPU,OP_FPOP,NONE,FRB,NONE,NONE,NONE,BF,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,5/0=ftsqrt,X,
-0000100110,FPU,OP_FPOP,NONE,NONE,NONE,NONE,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,1/6=mtfsb1,X,
-0001000110,FPU,OP_FPOP,NONE,NONE,NONE,NONE,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,2/6=mtfsb0,X,
-0010000110,FPU,OP_FPOP,NONE,NONE,NONE,NONE,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,4/6=mtfsfi,X,
+0000100110,FPU,OP_FPOP,NONE,NONE,NONE,NONE,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,1/6=mtfsb1,X,
+0001000110,FPU,OP_FPOP,NONE,NONE,NONE,NONE,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,2/6=mtfsb0,X,
+0010000110,FPU,OP_FPOP,NONE,NONE,NONE,NONE,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,4/6=mtfsfi,X,
 1101000110,FPU,OP_FPOP_I,FRA,FRB,NONE,FRT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,26/6=fmrgow,X,
 1111000110,FPU,OP_FPOP_I,FRA,FRB,NONE,FRT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,30/6=fmrgew,X,
-1001000111,FPU,OP_FPOP_I,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,18/7=mffs,X,
-1011000111,FPU,OP_FPOP_I,NONE,FRB,NONE,NONE,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,22/7=mtfsf,X,
-0000001000,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,0/8=fcpsgn,X,
-0000101000,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,1/8=fneg,X,
-0001001000,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,2/8=fmr,X,
-0010001000,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,4/8=fnabs,X,
-0100001000,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,8/8=fabs,X,
-0110001000,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,12/8=frin,X,
-0110101000,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,13/8=friz,X,
-0111001000,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,14/8=frip,X,
-0111101000,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,15/8=frim,X,
-0000001100,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,0/12=frsp,X,
-0000001110,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,0/14=fctiw,X,
-0010001110,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,4/14=fctiwu,X,
-1100101110,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,25/14=fctid,X,
-1101001110,FPU,OP_FPOP_I,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,26/14=fcfid,X,
-1110101110,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,29/14=fctidu,X,
-1111001110,FPU,OP_FPOP_I,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,30/14=fcfidu,X,
-0000001111,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,0/15=fctiwz,X,
-0010001111,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,4/15=fctiwuz,X,
-1100101111,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,25/15=fctidz,X,
-1110101111,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,29/15=fctiduz,X,
------10010,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,fdiv,A,
------10100,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,fsub,A,
------10101,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,fadd,A,
------10110,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,fsqrt,A,
------10111,FPU,OP_FPOP,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,fsel,A,
------11000,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,fre,A,
------11001,FPU,OP_FPOP,FRA,NONE,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,fmul,A,
------11010,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,frsqrte,A,
------11100,FPU,OP_FPOP,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,fmsub,A,
------11101,FPU,OP_FPOP,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,fmadd,A,
------11110,FPU,OP_FPOP,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,fnmsub,A,
------11111,FPU,OP_FPOP,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,fnmadd,A,
+1001000111,FPU,OP_FPOP_I,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,18/7=mffs,X,
+1011000111,FPU,OP_FPOP_I,NONE,FRB,NONE,NONE,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,22/7=mtfsf,X,
+0000001000,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,0/8=fcpsgn,X,
+0000101000,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,1/8=fneg,X,
+0001001000,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,2/8=fmr,X,
+0010001000,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,4/8=fnabs,X,
+0100001000,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,8/8=fabs,X,
+0110001000,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,12/8=frin,X,
+0110101000,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,13/8=friz,X,
+0111001000,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,14/8=frip,X,
+0111101000,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,15/8=frim,X,
+0000001100,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,0/12=frsp,X,
+0000001110,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,0/14=fctiw,X,
+0010001110,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,4/14=fctiwu,X,
+1100101110,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,25/14=fctid,X,
+1101001110,FPU,OP_FPOP_I,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,26/14=fcfid,X,
+1110101110,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,29/14=fctidu,X,
+1111001110,FPU,OP_FPOP_I,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,30/14=fcfidu,X,
+0000001111,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,0/15=fctiwz,X,
+0010001111,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,4/15=fctiwuz,X,
+1100101111,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,25/15=fctidz,X,
+1110101111,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,29/15=fctiduz,X,
+-----10010,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,fdiv,A,
+-----10100,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,fsub,A,
+-----10101,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,fadd,A,
+-----10110,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,fsqrt,A,
+-----10111,FPU,OP_FPOP,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,fsel,A,
+-----11000,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,fre,A,
+-----11001,FPU,OP_FPOP,FRA,NONE,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,fmul,A,
+-----11010,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,frsqrte,A,
+-----11100,FPU,OP_FPOP,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,fmsub,A,
+-----11101,FPU,OP_FPOP,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,fmadd,A,
+-----11110,FPU,OP_FPOP,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,fnmsub,A,
+-----11111,FPU,OP_FPOP,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,fnmadd,A,