From: Marek Olšák <marek.olsak@amd.com>
Date: Thu, 8 Sep 2016 18:15:51 +0000 (+0200)
Subject: radeonsi: flush TC L2 before using a compute indirect buffer
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=08bcbfdc07ed6ba371998b00deb7a2a67357c6af;p=mesa.git

radeonsi: flush TC L2 before using a compute indirect buffer

There is no known test for this.

Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
---

diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c
index f43c616b272..d9882141444 100644
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -464,10 +464,18 @@ static void si_launch_grid(
 
 	/* Add buffer sizes for memory checking in need_cs_space. */
 	r600_context_add_resource_size(ctx, &program->shader.bo->b.b);
-	if (info->indirect)
-		r600_context_add_resource_size(ctx, info->indirect);
 	/* TODO: add the scratch buffer */
 
+	if (info->indirect) {
+		r600_context_add_resource_size(ctx, info->indirect);
+
+		/* The hw doesn't read the indirect buffer via TC L2. */
+		if (r600_resource(info->indirect)->TC_L2_dirty) {
+			sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
+			r600_resource(info->indirect)->TC_L2_dirty = false;
+		}
+	}
+
 	si_need_cs_space(sctx);
 
 	if (!sctx->cs_shader_state.initialized)