From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 30 May 2020 16:01:03 +0000 (-0700)
Subject: abc9_ops: fix comment
X-Git-Tag: working-ls180~507^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=08d9703ecba375ba5588cbbb9dbf0f86757f6bb5;p=yosys.git

abc9_ops: fix comment
---

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index b4d4b77d5..2b79e1064 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -1439,7 +1439,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
 	//   treated as being "free"), in particular driving primary
 	//   outputs (real primary outputs, or cells treated as blackboxes)
 	//   or driving box inputs.
-	// Instead of just mapping those $_NOT_ gates into 2-input $lut-s
+	// Instead of just mapping those $_NOT_ gates into 1-input $lut-s
 	//   at an area and delay cost, see if it is possible to push
 	//   this $_NOT_ into the driving LUT, or into all sink LUTs.
 	// When this is not possible, (i.e. this signal drives two primary