From: lkcl <lkcl@web>
Date: Sat, 4 Jun 2022 12:24:11 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1990
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=08fb2c432cd0b0d3d16f2c7dba4186baad8424b6;p=libreriscv.git

---

diff --git a/openpower/sv/remap.mdwn b/openpower/sv/remap.mdwn
index 3f02ebfda..179d6b0cc 100644
--- a/openpower/sv/remap.mdwn
+++ b/openpower/sv/remap.mdwn
@@ -62,6 +62,17 @@ general-purpose remapping the `Indexed` REMAP may be deployed.
 * `sv.instruction` where any register marked as Vectorised will be
   REMAPPED.
 
+The following illustrative example multiplies a 3x4 and a 5x3
+matrix to create
+a 5x4 result:
+
+    svshape 5, 4, 3, 0, 0
+    svremap 31, 1, 2, 3, 0, 0, 0, 0
+    sv.fmadds 0.v, 8.v, 16.v, 0.v
+
+The example may be executed as a unit test and demo,
+[here](https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/test_caller_svp64_matrix.py;h=c15479db9a36055166b6b023c7495f9ca3637333;hb=a17a252e474d5d5bf34026c25a19682e3f2015c3#l94)
+
 # REMAP SPR
 
 | 0  | 2  | 4  | 6  | 8  | 10.14 | 15..23 |