From: Kugan Vivekanandarajah <kuganv@linaro.org>
Date: Sat, 30 Mar 2019 04:24:22 +0000 (+0000)
Subject: re PR rtl-optimization/89862 (LTO bootstrap fails for ARM)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=09062aa45c273ef70653be0f2541af1923a37bac;p=gcc.git

re PR rtl-optimization/89862 (LTO bootstrap fails for ARM)


2019-03-29  Kugan Vivekanandarajah  <kuganv@linaro.org>
	    Eric Botcazou  <ebotcazou@adacore.com>

	PR rtl-optimization/89862
	* rtl.h (word_register_operation_p): Exclude CONST_INT from operations
	that operates on the full registers for WORD_REGISTER_OPERATIONS
	architectures.


Co-Authored-By: Eric Botcazou <ebotcazou@adacore.com>

From-SVN: r270030
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index a9b1ee79632..13678514916 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2019-03-29  Kugan Vivekanandarajah  <kuganv@linaro.org>
+	    Eric Botcazou  <ebotcazou@adacore.com>
+
+	PR rtl-optimization/89862
+	* rtl.h (word_register_operation_p): Exclude CONST_INT from operations
+	that operates on the full registers for WORD_REGISTER_OPERATIONS
+	architectures.
+
 2019-03-29  Jim Wilson  <jimw@sifive.com>
 
 	* common/config/riscv/riscv-common.c (riscv_parse_arch_string):
diff --git a/gcc/rtl.h b/gcc/rtl.h
index 1a021fbec5f..b4a906f9181 100644
--- a/gcc/rtl.h
+++ b/gcc/rtl.h
@@ -4400,6 +4400,7 @@ word_register_operation_p (const_rtx x)
 {
   switch (GET_CODE (x))
     {
+    case CONST_INT:
     case ROTATE:
     case ROTATERT:
     case SIGN_EXTRACT: